Standard Cell Structure and Diffusion Reordering for Block Area Reduction in Double Diffusion Break FinFET Process

Abstract

This paper proposes standard cell layout style to reduce the block area in double-diffusion break FinFET process. The first generation of FinFET process technology requires a double-diffusion break to shutdown the leakage current under the dummy gate. Double-diffusion break at the edge of the standard cell requires two additional unit cells for the dummy gates and it results in a large block area. We propose a FinFET cell layout style which VDD/VSS diffusions can be shared with adjacent cells. The proposed layout structure places the VDD/VSS-diffusions at the cell edge to place these nodes adjacently, and it eliminates the use of a double diffusion break. We also propose a diffusion reorder algorithm to improve the use of common potential node sharing. Experimental results show that the proposed cell library with a new layout style and reordering algorithm achieves an 8.39% area reduction in on average.