A Satisfiability Algorithm for Synchronous Boolean Circuits

Abstract

The circuit satisfiability problem has been intensively studied since Ryan Williams showed a connection between the problem and lower bounds for circuit complexity. In this letter, we present a #SAT algorithm for synchronous Boolean circuits of n inputs and s gates in time $2^{n\left(1 - \frac{1}{2^{O(s/n)}}\right)}$ if s=o(n log n).