IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Test and Verification of VLSIs
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
Masayuki ARAISatoshi FUKUMOTOKazuhiko IWASAKI
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2008 Volume E91.D Issue 3 Pages 720-725

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Abstract
In this paper, we propose a scheme for test data reduction which uses broadcaster along with bit-flipping circuit. The proposed scheme can reduce test data without degrading the fault coverage of ATPG, and without requiring or modifying the arrangement of CUT. We theoretically analyze the test data size by the proposed scheme. The numerical examples obtained by the analysis and experimental results show that our scheme can effectively reduce test data if the care-bit rate is not so much low according to the number of scan chains. We also discuss the hybrid scheme of random-pattern-based flipping and single-input-based flipping.
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© 2008 The Institute of Electronics, Information and Communication Engineers
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