This paper proposes a new N-multilevel topologies for T-type inverter. The proposed topologies constitute the single bridge legs with the shape of the rotated character “T” and a variable direct current-link circuit. The proposed topologies present higher efficiency and lower number of components compared with NPC topologies and nested multilevel topologies. Also, other topologies have been compared in terms of reduced number of diodes, switches, flying capacitors, and DC supplies. The optimized staircase modulation technique is used to obtain voltage waveforms with high quality and superior output voltages. Furthermore, the principles of the proposed topologies were validated via simulations and experiments.
This paper presents a novel planar matching load for traveling-wave-fed substrate integrated waveguide (SIW) slot arrays. The load consists of a planar grounded coplanar waveguide (GCPW) matching load and a planar GCPW to SIW transition which makes the GCPW matching load compatible with the SIW. In the GCPW matching load a high frequency resistor is used to dissipate the remaining power. A traveling-wave-fed SIW slot array with the novel load is designed, fabricated and measured. The measurement results show the proposed planar matching load performs well over a wide band 24.2–26.0 GHz, and reflection coefficient and side lobe level (SLL) of the array is significantly reduced comparing with the array with no load.
A low-profile circularly-polarized (CP) antenna with broad axial-ratio (AR) beamwidth is presented by loading with artificial magnetic conductor (AMC). The antenna consists of a couple of modified dipoles with four crossed symmetrical fan-shaped arms and a magneto-electric (ME) dipole equipped to broaden AR beamwidth. One AMC consists of 5 × 5 units is integrated to reduce the backward scattering wave and simultaneously ensures a low profile. The measured results of one fabricated type reveal that the AMC-integrated antenna accomplishes a wide 3-dB AR beamwidth (>135°) and exhibits a low-profile property with the height of 0.054λ0, which can be applied in the BeiDou Satellite System (BDS).
The accurate extraction of inter-electrode coupling capacitances (IECCs) is a difficult but important issue in small-signal modeling of highly scaled transistors. In this paper, a new method of determining the IECCs for deep-submicron aluminium gallium nitride/gallium nitride (AlGaN/GaN) high electron–mobility transistors (HEMTs) is proposed. The method uses the pinch-off S-parameters under large drain bias to eliminate the influence of intrinsic capacitance on IECCs extraction, thereby determining the reliable starting value of IECCs. Compared with the conventional method, this method not only greatly reduces the parameter searching range in final value optimization but also avoids the non-physical extraction value for intrinsic parameters. Using this method, we build a small-signal model for a 0.15 µm gate-length GaN HEMT. The measured data show that this method has high precision and can be applied to the modeling of millimeter-wave GaN HEMTs.
A differential PA (power amplifier) with a novel structure is introduced in this paper. This PA is constructed with single ended input and balanced output. It is fabricated in 2 µm InGaP/GaAs HBT technology. The small-signal bandwidth of this PA covers from 1.5 GHz to 2.7 GHz. 34 dBm P−1dB (1 dB gain-compression power) and 45% PAE (power added efficiency) is achieved at 2.1 GHz. Moreover, the quiescent power dissipation is 400 mW with 12 V supply.
Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.
In this paper, we propose a CGSA (Coarse Grained Spatial Architecture) which processes different kinds of convolution with high performance and low energy consumption. The architecture’s 16 coarse grained parallel processing units achieve a peak 152 GOPS running at 500 MHz by exploiting local data reuse of image data, feature map data and filter weights. It achieves 99 frames/s on the convolutional layers of the AlexNet benchmark, consuming 264 mW working at 500 MHz and 1 V. We evaluated the architecture by comparing some recent CNN’s accelerators. The evaluation result shows that the proposed architecture achieves 3× energy efficiency and 3.5× area efficiency than existing work of the similar architecture and technology proposed by Chen.
This letter proposes a novel sub-1 V voltage-current (V-I) converter-based voltage-controlled oscillator (VCO) for the low-voltage phase-locked loop (PLL) of display driver integrated circuit. The proposed VCO improves on the state-of-the-art V-I converter-based VCO, which uses a first-order current equation for the VCO, to achieve linear voltage-to-frequency gain of the VCO (KVCO) over the full range of the control voltage, from the ground to the supply voltage in sub-1 V CMOS technology. To obtain a full supply transition output with high immunity to noise, the improved VCO is designed to control the gate voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), instead of the supply voltage of a ring oscillator without significant area overhead. As a result, the proposed VCO obtains a linear KVCO with a wider control voltage range than a conventional VCO when its tuning range is from 1.25 to 3.6 GHz in a 65 nm 1.0 V CMOS technology.
There is a growing demand for embedded non-volatile memory (eNVM) in Internet of Things (IoTs). Phase change memory (PCM) is a promising candidate for next generation eNVM with excellent CMOS process compatibility. Deep trench isolation (DTI) process is one of the extra steps to generate the diode selectors for PCM cells under 40 nm CMOS process. In this paper, we propose a 40 nm Non-volatile Standard cell Library (NSL) by reusing the DTI process to minimize the space among active areas. Thus, benefit from the embedded PCM (emPCM) process, the area of logic circuits can be reduced by using NSL. To verify the validity of the NSL, four ring oscillators are fabricated by using the normal standard cell library and NSL. The measured results show that the circuits by NSL work well and there is almost no performance sacrifice.
A low transmission loss, simple mechanical structure, and broadband waveguide-to-microstrip line transducer has been developed with a polytetrafluoroethylene printed circuit board. This can fully cover the V-band, E-band, and W-band, and the transmission losses are typically 0.68 dB, 0.86 dB, and 0.78 dB, respectively, at the center frequency of each band. The transducer in the W-band was already implemented in a W-band 2nd-order harmonic mixer. In this letter, we report the development of the millimeter-wave waveguide-to-microstrip line transducer.
As storage interfaces have begun to employ high-speed signals and complex protocols, it has become increasingly difficult to ensure correct interactions between hosts and their storage. Correctness verification often requires the acquisition and thorough inspection of signals running at the interface. However, increases in interface signaling frequency may aggravate misalignment between sampling clocks and signals as well as among multiple signals, rendering signal acquisition and inspection difficult. To address this problem, this paper proposes a dynamic phase alignment scheme that can be used within a signal acquisition system. The proposed scheme was implemented on a Field-Programmable Gate Array (FPGA) board and was verified to successfully capture interface signals.
This paper proposes an Energy-Efficient Reconfigurable Architecture (E-ERA) for Recurrent Neural Networks (RNNs). In E-ERA, reconfigurable computing arrays with approximate multipliers and dynamically adaptive accuracy controlling mechanism are implemented to achieve high energy efficiency. The E-ERA prototype is implemented on TSMC 45 nm process. Experimental results show that, comparing with traditional designs, the power consumption of E-ERA is reduced by 28.6%∼52.3%, with only 5.3%∼9.2% loss in accuracy. Compared with state-of-the-art architectures, E-ERA outperforms up to 1.78X in power efficiency and can achieve 304 GOPS/W when processing RNNs for speech recognition.
A novel Z-source three-level inverter based on coupled inductors is proposed. The two inductors in traditional Z-source impedance network are replaced by two coupled inductors. The operating principle is described and the equations of boost factor and voltage stresses are deduced. Comparisons are made with other Z-source three-level inverters, especially the multicell switched inductor Z-source three-level inverter. The two topologies have same boost factor if a specific condition is met, but the proposed inverter uses less components and therefore the reliability is improved. SVPWM method for conventional three-level NPC inverter is easy to apply to the novel inverter after a simple modification. Simulations are conducted to verify the theoretical analysis.
In this brief, we propose a novel method which realizes conflict-free strategy in memory-based FFT, of which the hardware complexity is simplified, since only a few extra registers are needed and the control logic is identical in all stages. In addition, we present a modified signal flow graph to fit for the proposed conflict-free strategy. The modified signal flow graph derives from the mixed-radix signal flow graph and has constant geometry property. Furthermore, continuous-flow is adopted to increase the throughput. Thus, the proposed FFT processor has better performance compared with the previous memory-based FFT processors. Simulation result shows that for the proposed 8 to 2048-point FFT processor, the maximum frequency is 400 MHz by using a 65-nm CMOS technology, and the area is 0.45 mm2 in the same condition.
This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 × 3.35 mm2 chip, designed with 40 nm CMOS technology, contains 8.22 M gates and 5 Mb SRAM in the chip of 3.35 × 3.35 mm2. The simulated power consumption at 133 MHz were 528 mW and 702 mW at the slow process condition (SS, 0.81 V, −40°C) and typical process condition (TT, 0.9 V, 25°C), respectively.
This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2. The total power consumption is 16 mW.
A low-cost, compact 5-Gbps fully integrated CMOS optical receiver without equalizer is fabricated in this paper in a standard 0.18-µm CMOS technology. The measured responsivity of the DNW-strip-SMPD operating in avalanche mode is 1.4 A/W, while the bandwidth is 2.9 GHz with 11.6 V reverse bias voltage. The application for 5-Gbps very-short-reach optoelectronic integrated circuit (OEIC) receiver with a bit-error rate <10−12 at incident optical power of −4 dBm has been experimentally demonstrated. The core chip area of the OEIC receiver is 0.736 mm by 0.515 mm, and it consumes 96 mW from the 1.8 V supply. Our OEIC receiver has the smallest area and the lowest power consumption in the OEIC receivers reported so far fabricated in 0.18-µm CMOS technology.
The study of battery behaviors has become a necessity in order to design efficient battery management systems for large-scale energy storage applications. This paper developed an open-circuit-voltage (OCV) characterization system implemented with sequential-control algorithms to study the OCV characteristics in Mn-type Li-ion batteries and their electrode properties regarding the phase-transition mechanisms. Differential voltage (DV) and incremental capacity (IC) techniques are applied for analyzing the phase-transition behaviors. Based on the changes of DV and IC characteristics for the OCV, the phase-transitions are discussed and evaluated to understand electrochemical changes and deterioration mechanisms in the batteries during cycling operations.
In this paper, a high-order Sigma-Delta (ΣΔ) modulator in a standard 0.5 µm CMOS technology for a tunneling magneto-resistance sensor (TMR) is presented. The digital output is attained by the interface circuit based on a low-noise chopper front-end and a back-end forth-order Sigma-Delta modulator. The low-noise front-end detection circuit is proposed with correlated double sampling (CDS) technique to eliminate the 1/f noise and offset of operational amplifier. The even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.5 µm CMOS process and the active circuit area is about 4 × 3 mm2. The modulator chip consumes 9.6 mW from a 5 V supply and the sampling frequency is 6.4 MHz. The modulator can achieve a signal-to-noise ratio (SNR) of 121 dB, an effective number of bits 19.85 bits and a harmonic distortion of 113 dB.
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