The analog-to-information converter (AIC) based on compressed sensing samples the analog signals at sub-Nyquist rate. This paper presents a low-cost hardware implementation of AIC based on random demodulation. The realization consists of a sampling part and a transmission part, which are connected by using a FPGA chip. In the former, the input analog signal is modulated with a pseudo-random sequence, and sampled with sub-Nyquist rate to obtain low-dimensional measurements. In the latter, the measurements are transmitted with user datagram protocol to the computer. The experimental results demonstrate the effectiveness of the hardware implementation.
In this paper, a bandpass reconfigurable frequency selective surface (FSS) with high isolation at passband, which can reconfigure the operating frequency by using a PIN diode for the X-band, was designed. The proposed surface is composed of four-legged loaded elements, inductance stubs, and a bias grid to supply power. By controlling the electrical length of the unit cell using the forward bias and zero bias of the PIN diode located between the cross-shaped pattern and the stub, the operating frequency can be reconfigured. By controlling the stub length, the switching range of the operating frequency can be controlled. Based on the design results, two types of reconfigurable FSS were constructed, and their measured transmission losses, obtained using the rectangular waveguides WR-75 and WR-90, were compared with simulation results. The comparison showed very similar results.
A CMOS 3–5 GHz ultra-wideband (UWB) low-noise amplifier (LNA) with an integrated active interferer rejection is presented. The LNA eliminates the out-band 2.4 GHz interferers without deteriorating the input matching and gain by employing the active tunable bandpass feedback loop to produce a notch at the interferer frequencies. The proposed LNA is fabricated using a 0.18 µm CMOS process. The 3–5 GHz UWB LNA with the integrated bandpass feedback loop achieves an out-band 2.4 GHz interferer rejection of 29.2 dB, a power gain of 15.3 dB, and a minimum noise figure of 4 dB with a power consumption of 9.1 mW.
This paper presents the design of a low noise Schottky-diode 190–240 GHz subharmonic mixer (SHM). The embedding impedance condition for the diodes to yield optimum circuit performance is primarily determined. It is achieved using the computer-aided design (CAD) load-pull techniques by taking into account the high-frequency parasitic effects caused by the diode chip geometry. By knowing this condition, the design procedure of the mixer circuitry is expedited. The design effectiveness of the proposed methodology is experimentally validated by the good agreement between the design predictions and the measured results of the mixer performance. Y-factor measurements show that the mixer exhibits the double side band (DSB) noise temperature lower than 1500 K and DSB conversion loss less than 10 dB over the 190–240 GHz frequency range, with the DSB noise temperature and conversion loss at 220 GHz of 800 K and 7 dB respectively.
This work proposes coupled inductor-buck (CI-B) power factor correction (PFC) LED driver. As compared with conventional buck converters, the proposed CI-B PFC converter has several advantages such as; high step-down conversion, reduced total harmonic distortion (THD), increased efficiency, achieves high power factor (PF), reduced current/voltage stress of switch/diode, and effective switch utilization factor. The proposed converter is designed to operate in discontinuous current mode (DCM) to achieve high power factor (PF) and low THD to comply IEC 61000-3-2 class C standards. In addition, a simple one-loop voltage mode controller (VMC) is implemented to achieve the desired regulated output voltage. A proto-type of 16 Watt converter is built and experimental validations are presented.
In this paper, an improved computation method of maximal Lyapunov character exponent (mLCE) is proposed to analyze the nonlinear dynamic behaviors in the V2C-mode-controlled buck converter. In this method, a compensation algorithm of the Jacobi matrix at the non-differentiable point is given after analyzing the geometric relationship between the two subsystems on both sides of the switching surface. Besides, according to the fact that the chaos control can be realized by increasing the correlation of system state variables, the coupling strength ε is introduced to the system of V2C-mode-controlled buck converter and optimized by particle swarm optimization (PSO), in order to eliminate the recognized chaotic behaviors. Finally, the effectiveness of the given method is validated by a simulation and an experimental setup.
To meet the stringent spectral mask requirement of IEEE 802.15.6, a novel spectral shaping buffer and a new automatic calibration are proposed in this paper. By introducing a floating current into buffer, second order intermodulation product (IM2) is cancelled at output. To calibrate buffer, analog signal processing methods for average power extraction of residual IM2 and accurate quantization are presented, along with error-tolerant decision making logic. A sample human body communication (HBC) transmitter is designed in 0.13 µm CMOS process. Simulation results show spectral mask is suppressed below −120 dBr, satisfying the IEEE 802.15.6 standard specification.
We demonstrate a tunable distributed Bragg reflector (DBR) laser diode operating in the 2-µm region. A strained InGaAs multi-quantum well is used for the active region, and InGaAs is used for the passive region in the 2-µm DBR laser. The fabricated DBR laser emits a single-mode continuous wave at 2.02 µm, and the output power exceeds 6 mW at room temperature. A wavelength tuning range of about 10 nm is achieved by controlling of injection currents to the DBR regions.
In this study, a paper-based reconfigurable frequency selective surface (FSS) that can be applied as wallpaper inside buildings to control the indoor spectrum was designed using the ink-jet printing method. The designed paper-based FSS uses a PIN diode to block 5 GHz band signals in the OFF condition and to transmit the signals in the ON condition, offering frequency characteristics stable to polarization and incident angles. To verify the operation of the designed FSS, the FSS was printed on a 0.2 mm thick paper using the ink-jet printing method by attaching a PIN diode using a conductive adhesive to manufacture the FSS with a switching function. It was confirmed that the measured frequency transmission characteristics according to the switching operation corresponded to the calculated results, and stability was exhibited for polarization and incident angles.
Frequency response mismatches (FRMs) in time-interleaved analog-to-digital converters (TIADCs) generate undesired spurs degrading the performance of TIADCs. This paper introduces a digital calibration method for the FRM in M-channel TIADCs (M-TIADCs). This method exploits fixed differentiator finite-impulse response (FIR) filters and the Hadamard transform to reconstruct the mismatch induced error signal. The mismatch parameters are estimated utilizing a short training signal and the least square (LS) method. Our method is simpler in terms of implementation compared with conventional methods as cumbersome time-varying filters, complex signal processing and front-end hardware modifications are avoided. Numerical simulation results demonstrate the efficacy and efficiency of the proposed method.
We propose a new quantum communication scheme using quantum coherent states. In our scheme, classical information and the secret key are transmitted simultaneously without any loss of secret key rate performance, while only the secret key is transmitted in the conventional protocol. In our protocol, classical information is first modulated by pulse amplitude modulation (PAM). The secret key is then mapped by random Gaussian modulation and is added to the PAM symbol. The receiver decodes the classical information, treating the Gaussian signal as additive noise. The classical symbol is discarded from the received state after successive decoding of the classical information, and the secret key is then distilled by conventional protocol. We demonstrate that after the classical symbol is discarded, the remaining system is identical to the conventional quantum key distribution system. Our proposed scheme provides the same secret key rate as that of the conventional quantum key distribution system and provides an additional data rate of classical information.
EDAC (Error Detection and Correction) techniques guarantee PVT variation safety by dynamically fixing timing error instead of providing static margins. However, previous EDAC works introduce additional area, power and performance penalty, thus the benefit from timing margin eliminating is limited. In this paper, we propose a novel EDAC Flip-Flop, EDSU, with ultra-low area overhead and nearly zero performance penalty. EDSU utilizes only two more transistors than conventional D-Flip Flop and can correct timing error simultaneously with detection. The ultra-lightweight property can obviously reduce area overhead and clock load, thus improve the variation tolerance ability and energy efficiency. EDSU is implemented in a commercial processor at SMIC 40 nm technology to evaluate its benefits. Simulation result shows EDSU inserted system gains 12.5% more performance at fixed voltage, 25% more variation tolerance and 10.5% energy saving at fixed throughput than state-of-art EDAC work.
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