In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.

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In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register architectures (RDR architectures) have been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidate operations for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximal allowable inter-island distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously based on the results of the two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our proposed algorithm reduces the latency by up to 40.0% compared to the original approach, and by up to 25.0% compared to a conventional approach. Our algorithm also reduces the number of registers and the number of multiplexers compared to the conventional approaches in some cases.

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In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.

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Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.

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As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring the middle points, or check points of several speed-paths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

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The coarse-grained reconfigurable architecture (CGRA) is a promising computing platform that provides both high performance and high power-efficiency. The computation-intensive portions of an application (e.g. loop nests) are often mapped onto CGRA for acceleration. However, mapping loop nests onto CGRA efficiently is quite a challenge due to the special characteristics of CGRA. To optimize the mapping of loop nests onto CGRA, this paper makes three contributions: i) Establishing a precise performance model of mapping loop nests onto CGRA, ii) Formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, iii) Extracting an efficient heuristic algorithm and building a complete flow of mapping loop nests onto CGRA (PolyMAP). Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 27% on average, as compared to the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

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Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.

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As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.

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Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

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As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.

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We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64dB is achievable at an input signal frequency of 10kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

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In this paper, we propose Affine Combination Lattice Algorithm (ACLA) as a new lattice-based adaptive notch filtering algorithm. The ACLA makes use of the affine combination of Regalia's Simplified Lattice Algorithm (SLA) and Lattice Gradient Algorithm (LGA). It is proved that the ACLA has faster convergence speed than the conventional lattice-based algorithms. We conduct this proof by means of theoretical analysis of the mean update term. Specifically, we show that the mean update term of the ACLA is always larger than that of the conventional algorithms. Simulation examples demonstrate the validity of this analytical result and the utility of the ACLA. In addition, we also derive the step-size bound for the ACLA. Furthermore, we show that this step-size bound is characterized by the gradient of the mean update term.

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This paper proposes an updating state dependent disturbance observer (USDDOB) to reject position dependent disturbances when parameters vary slowly, and input and output are time-delayed. To reject the effects of resultant slowly-varying position dependent disturbances, the USDDOB uses the control method of the state dependent disturbance observer (SDDOB) and time-invariance approximation. The USDDOB and a main proportional integral (PI) controller constitute a robust controller. Simulations and experiments using a 1-degree-of-freedom (1-DOF) tilted planar robot show the effectiveness of the proposed method.

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It is not easy to provide energy supply based on renewable energy enough to satisfy energy demand anytime and anywhere because the amount of renewable energy depends on geographical conditions and the time of day. In order to maximize the satisfaction of energy demand by renewable energy, surplus energy generated with renewable energy should be stored in batteries, and transmitted to electric loads with high demand somewhere in the electricity system. This paper proposes a novel autonomous decentralized mechanism of energy interchanges between distributed batteries on the basis of the diffusion equation and MCMC (Markov Chain Monte Carlo) for realizing energy supply appropriately for energy demand. Experimental results show that the proposed mechanism effectively works under several situations. Moreover, we discuss a method to easily estimate the behavior of the entire system by each node with the proposed mechanism, and the application potentiality of this estimating method to an efficient method working with non-renewable generators while minimizing the dependence of non-renewable energy, and an incentive mechanism to prevent monopolizing energy in systems.

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In recent years, applications of complex-valued neural networks have become wide spread. Quaternions are an extension of complex numbers, and neural networks with quaternions have been proposed. Because quaternion algebra is non-commutative algebra, we can consider two orders of multiplication to calculate weighted input. However, both orders provide almost the same performance. We propose hybrid quaternionic Hopfield neural networks, which have both orders of multiplication. Using computer simulations, we show that these networks outperformed conventional quaternionic Hopfield neural networks in noise tolerance. We discuss why hybrid quaternionic Hopfield neural networks improve noise tolerance from the standpoint of rotational invariance.

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Multiple-way (N-way) asynchronous arbitration is an important issue in asynchronous system design. In this paper, novel implementation methods of N-way asynchronous arbiters are presented. We first present N-way rectangle mesh arbiters using 2-way mutual exclusion elements. Then, N-way token-ring arbiters based on the non-return-to-zero signaling is also presented. The former can issue grant signals with the same percentage for all the arriving request signals while the latency is proportional to the number of inputs. The latter can achieve low latency and low energy arbitration for a heavy workload environment and a large number of inputs. In this paper, we compare their performances using the 28nm FD-SOI process technologies qualitatively and quantitatively.

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This paper presents an information hiding method for DNA steganography with which a massive amount of data can be hidden in a noncoding strand. Our method maps the encrypted data to the DNA sequence using a numerical mapping table, before concealing it in the noncoding sequence using a secret key comprising sector length and the random number generator's seed. Our encoding algorithm is sector-based and reference dependent. Using modular arithmetic, we created a unique binary-base translation for every sector. By conducting a simulation study, we showed that our method could preserve amino acid information, extract hidden data without reference to the host DNA sequence, and detect the position of mutation error. Experimental results verified that our method produced higher data capacity than conventional methods, with a bpn (bit-per-nucleotide) value that ranged from approximately 1-2, depending on the selected sector length. Additionally, our novel method detected the positions of mutation errors by the presence of a parity base in each sector.

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A power allocation to active and reactive power in stochastic resonance is discussed for energy harvesting from noise. It is confirmed that active power can be increased at stochastic resonance, in the same way of the relationship between energy and phase at an appropriate setting in resonance.

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In this letter, high quality speech reconstruction approaches from Mel-frequency cepstral coefficients (MFCC) are presented. Taking into account of the nonnegative and sparse properties of the speech power spectrum, an alternating direction method of multipliers (ADMM) based nonnegative l₂ norm (NL₂) and weighted nonnegative l₂ norm (NWL₂) minimization approach is proposed to cope with the under-determined nature of the reconstruction problem. The phase spectrum is recovered by the well-known LSE-ISTFTM algorithm. Experimental results demonstrate that the NL₂ and NWL₂ approach substantially achieves better quality for reconstructed speech than the conventional l₂ norm minimization approach, it sounds very close to the original speech when using the high-resolution MFCC, the PESQ score reaches 4.0.

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In this paper, a design method for the infinite impulse response (IIR) filters using the particle swarm optimization (PSO) is developed. It is well-known that the updating in the PSO tends to stagnate around local minimums due to a strong search directivity. Recently, the asynchronous digenetic PSO with nonlinear dissipative term (N-AD-PSO) has been proposed as a purpose for a diverse search. Therefore, it can be expected that the stagnation can be avoided by the N-AD-PSO. However, there is no report that the N-AD-PSO has been applied to any realistic problems. In this paper, the N-AD-PSO is applied for the IIR filter design. Several examples are shown to clarify the effectiveness and the drawback of the proposed method.

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Recently, among MIMO-OFDM detection schemes, a lot of V-BLAST schemes have been suggested in order to achieve high data rate. Therefore signal detection of MIMO-OFDM system is important issue. In this letter, extended DFE detection scheme is proposed. According to simulation result, the extended DFE detection has similar performance with QRD-M detection but the complexity is about 24.02% of QRD-M detection. Therefore the proposed E-DFE detection can be efficiently used in MIMO-OFDM system.

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We address a robust algorithm for the interference-plus-noise covariance matrix reconstruction (RA-INCMR) against random arbitrary steering vector mismatches (RASVMs) of the interferences, which lead to substantial degradation of the original INCMR beamformer performance. Firstly, using the worst-case performance optimization (WCPO) criteria, we model these RASVMs as uncertainty sets and then propose the RA-INCMR to obtain the robust INCM (RINCM) based on the Robust Capon Beamforming (RCB) algorithm. Finally, we substitute the RINCM back into the original WCPO beamformer problem for the sample covariance matrix to formulate the new RA-INCM-WCPO beamformer problem. Simulation results demonstrate that the performance of the proposed beamformer is much better than the original INCMR beamformer when there exist RASVMs, especially at low signal-to-noise ratio (SNR).

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In emerging wearable sensor systems, it is crucial to save energy because these systems are severely energy-constrained. For making the sensors in these systems energy efficient, transmission power control (TPC) is widely used, and thus far, many TPC algorithms have been proposed in the literature. However, these TPC algorithms do not always work well in all wireless body channel conditions, which are capriciously varied due to diverse sensor environments such as sensor placements, body movements, and body locations. In this paper, we propose a simple TPC algorithm that quickly and stably approaches the optimal transmission power level and works well in all wearable sensor environments. We experimentally evaluated the proposed TPC algorithm and proved that it works well under all wireless body channel conditions.

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For the electric demand prediction problem, a modification mechanism of predicted demand data has been proposed in the previous work. In this paper, we analyze the performance of the modification mechanism in power balancing control. Then, we analytically derive an upper bound of the performance, which is characterized by system parameters and prediction precision.

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For systems with a delay in the input, the predictor method has been often used in state feedback controllers for system stabilization or regulation. In this letter, we show that for a chain of integrators with even an unknown input delay, a much simpler and memoryless controller is a good candidate for system regulation. With an adaptive gain-scaling factor, the proposed state feedback controller can deal with an unknown time-varying delay in the input. An example is given for illustration.

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Let r be an odd prime, such that r≥5 and r≠p, m be the order of r modulo p. Then, there exists a 2p^th root of unity in the extension field F_r^m. Let G(x) be the generating polynomial of the considered quaternary sequences over F_q[x] with q=r^m. By explicitly computing the number of zeros of the generating polynomial G(x) over F_r^m, we can determine the degree of the minimal polynomial, of the quaternary sequences which in turn represents the linear complexity. In this paper, we show that the minimal value of the linear complexity is equal to $ \frac{1}{2}(3p-1) $ which is more than p, the half of the period 2p. According to Berlekamp-Massey algorithm, these sequences viewed as enough good for the use in cryptography.

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We introduce a coding theoretic criterion for Yamamoto's strong security of the ramp secret sharing scheme. After that, by using it, we show the strong security of the strongly multiplicative ramp secret sharing proposed by Chen et al. in 2008.

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This paper considers a method for constructing good high-rate punctured convolutional codes through dual codes. A low-rate R=1/n convolutional code has a dual code identical to a punctured convolutional code with rate R=(n-1)/n. This implies that a low-rate R=1/n convolutional code encoder can help the search of punctured convolutional code encoders. This paper provides the procedures that obtain all the useful dual code encoders to a given CC with rate R=1/n easily, and the best PCC encoder with rate R=(n-1)/n among the encoders we derive from all the obtained dual code encoders. This paper also shows an example of the PCC the procedures obtain from some CC.

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In wireless sensor networks, or WSNs, a malicious node is able to cover itself by switching between good and bad behaviors. Even when running under a reputation mechanism, such a node can still behave maliciously now and then so long as its reputation is within the acceptable level. To address this inconsistent behavior issue, a combined approach of statistic reputation and time series is proposed in this study, in which the negative binomial reputation is applied to rate the nodes' reputation and concept of time series is borrowed to analyze the reputation results. Simulations show that the proposed method can effectively counter inconsistent behavior nodes and thus improves the overall system performance.

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The mode of intra prediction in H.264/AVC is encoded based on the most probable mode (MPM). To increase coding efficiency, the probability of the case that MPM is equal to coding mode of the current block should increase. In this paper we propose an efficient scheme to make MPM which is matched for the spatial direction property of pixels in the current block. Simulation results show that the proposed scheme gives significant coding gains when compared with the conventional techniques.

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