In this paper, an algorithm based on Taylor series expansion is proposed to calculate the logarithm (log₂x) of IEEE754 binary32 accuracy floating-point number by a multi-domain partitioning method. The general mantissa (1≤x<2) is multiplied by 2, 4, 8, … (or equivalently left-shifted by 1, 2, 3, … bits), the regions of (2≤x<4), (4≤x<8), (8≤x<16),… are considered, and Taylor-series expansion is applied. In those regions, the slope of f(x)=log₂ x with respect to x is gentle compared to the region of (1≤x<2), which reduces the required number of terms. We also consider the trade-offs among the numbers of additions, subtractions, and multiplications and Look-Up Table (LUT) size in hardware to select the best algorithm for the engineer's design and build the best hardware device.

As known to us all, L-shaped co-prime array (LCA) is a recently introduced two-dimensional (2-D) sparse array structure, which is extended from linear co-prime array (CA). Such sparse array geometry can be used for 2-D parameters estimation with higher degrees-of-freedom (DOF). However, in the scenario where several narrowband transmissions spread over a wide spectrum, existing technique based on LCA with Nyquist sampling may encounter a bottleneck for both analog and digital processing. To alleviate the burden of high-rate Nyquist sampling, a method of joint wideband spectrum and direction-of-arrival (DOA) estimation with compressed sampling based on LCA, which is recognized as LCA-based modulated wideband converter (MWC), is presented in this work. First, the received signal along each antenna is mixed to basebands, low-pass filtered and down-sampled to get the compressed sampling data. Then by constructing the virtual received data of 2-D difference coarray, we estimate the wideband spectrum and DOA jointly using two recovery methods where the first is a joint ESPRIT method and the other is a joint CS method. Numerical simulations illustrate the validity of the proposed LCA based MWC system and show the superiority.

This paper investigates the charging control strategy design problem of a large-scale plug-in electric vehicle (PEV) group, where each PEV aims to find an optimal charging strategy to minimize its own cost function. It should be noted that the collective behavior of the group is coupled in the individual cost function, which complicates the design of decentralized charging strategies. To obtain the decentralized charging strategy, a mean-field game (MFG) formulation is proposed where a penalty on collective consensus is embedded and a class of mean-field coupled time-varying stochastic systems is targeted for solving the MFG which involves the charging model of PEVs as a special case. Then, an augmented system with dimension extension and the policy iteration algorithm are proposed to solve the mean-field game problem for the class of mean-field coupled time-varying stochastic systems. Moreover, analysis of the convergence of proposed approach has been studied. Last, simulation is conducted to illustrate the effectiveness of the proposed MFG-based charging control strategy and shows that the charging control strategy can achieve desired mean-field state and impact to the power grid can be buffered.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware-Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features focusing on the structure of trigger circuits for machine-learning-based hardware-Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on a random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 64.2% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.8 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.

In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.

A unified construction for yielding optimal and balanced quaternary sequences from ideal/optimal balanced binary sequences was proposed by Zeng et al. In this paper, the linear complexity over finite field 𝔽₂, 𝔽₄ and Galois ring ℤ₄ of the quaternary sequences are discussed, respectively. The exact values of linear complexity of sequences obtained by Legendre sequence pair, twin-prime sequence pair and Hall's sextic sequence pair are derived.

We propose “Temporal Ensemble SSDLite,” a new method for video object detection that boosts accuracy while maintaining detection speed and energy consumption. Object detection for video is becoming increasingly important as a core part of applications in robotics, autonomous driving and many other promising fields. Many of these applications require high accuracy and speed to be viable, but are used in compute and energy restricted environments. Therefore, new methods that increase the overall performance of video object detection i.e., accuracy and speed have to be developed. To increase accuracy we use ensemble, the machine learning method of combining predictions of multiple different models. The drawback of ensemble is the increased computational cost which is proportional to the number of models used. We overcome this deficit by deploying our ensemble temporally, meaning we inference with only a single model at each frame, cycling through our ensemble of models at each frame. Then, we combine the predictions for the last N frames where N is the number of models in our ensemble through non-max-suppression. This is possible because close frames in a video are extremely similar due to temporal correlation. As a result, we increase accuracy through the ensemble while only inferencing a single model at each frame and therefore keeping the detection speed. To evaluate the proposal, we measure the accuracy, detection speed and energy consumption on the Google Edge TPU, a machine learning inference accelerator, with the Imagenet VID dataset. Our results demonstrate an accuracy boost of up to 4.9% while maintaining real-time detection speed and an energy consumption of 181mJ per image.

We consider a regulation problem for an uncertain chain of integrators with an unknown time-varying delay in the input. To deal with uncertain parameters and unknown delay, we propose an adaptive event-triggered controller with a dynamic gain. We show that the system is globally regulated and interexecution times are lower bounded. Moreover, we show that these lower bounds can be enlarged by adjusting a control parameter. An example is given for clear illustration.

Low-hit-zone frequency-hopping sequences (LHZ-FHSs) are frequency-hopping sequences with low Hamming correlation in a low-hit-zone (LHZ), which have important applications in quasi-synchronous communication systems. However, the strict quasi-synchronization may be hard to maintain at all times in practical FHMA networks, it is also necessary to minimize the Hamming correlation for time-shifts outside of the LHZ. The main objective of this letter is to propose a lower bound on the maximum correlation magnitude outside the low-hit-zone for LHZ-FHS sets. It turns out that the proposed bound is tight or almost tight in the sense that it can be achieved by some LHZ-FHS sets.