Fabrication of Sub-10 nm Metal Wire Circuits using Directed Self-Assembly of Block Copolymers

Tsukasa Azuma; Yuriko Seino; Hironobu Sato; Yusuke Kasahara; Katsutoshi Kobayashi; Hitoshi Kubota; Hideki Kanai; Katsuyoshi Kodera; Naoko Kihara; Yoshiaki Kawamonzen; Shinya Minegishi; Ken Miyagi; Hitoshi Yamano; Toshikatsu Tobana; Masayuki Shiraishi; Satoshi Nomura

doi:10.2494/photopolymer.29.647

Tsukasa Azuma, Yuriko Seino, Hironobu Sato, Yusuke Kasahara, Katsutoshi Kobayashi, Hitoshi Kubota, Hideki Kanai, Katsuyoshi Kodera, Naoko Kihara, Yoshiaki Kawamonzen, Shinya Minegishi, Ken Miyagi, Hitoshi Yamano, Toshikatsu Tobana, Masayuki Shiraishi, Satoshi Nomura

Author information

Tsukasa Azuma
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Yuriko Seino
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Hironobu Sato
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Yusuke Kasahara
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Katsutoshi Kobayashi
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Hitoshi Kubota
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Hideki Kanai
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Katsuyoshi Kodera
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Naoko Kihara
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Yoshiaki Kawamonzen
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Shinya Minegishi
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Ken Miyagi
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Hitoshi Yamano
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Toshikatsu Tobana
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Masayuki Shiraishi
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)
Satoshi Nomura
DSA Research Department, EUVL Infrastructure Development Center, Inc. (EIDEC)

Keywords: lithography, sub-10 nm, metal wire circuit, directed self-assembly, block copolymer

JOURNAL FREE ACCESS

2016 Volume 29 Issue 5 Pages 647-652

DOI https://doi.org/10.2494/photopolymer.29.647

Details

Abstract

A novel half-pitch (HP) 10 nm physical-epitaxial frequency multiplication process using a high chi (χ) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrically open and short process level-test element group (PL-TEG) yield verification of sub-10 nm metal wire circuits fabricated using the HP 10 nm physical-epitaxial frequency multiplication process was carried out on a 300 mm wafer. The electrically open and short PL-TEG yield verification revealed the viability of the HP 10 nm physical-epitaxial frequency multiplication process from the perspective of the total practical performance including critical dimension control, defect control, pattern placement error, space width roughness, space edge roughness, and process windows in the pattern transfer process.

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