IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A low-jitter phase-interpolation DDS using dual-slope integration
Hsin-Chuan ChenJen-Shiun Chiang
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2004 Volume 1 Issue 12 Pages 333-338

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Abstract

In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.

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© 2004 by The Institute of Electronics, Information and Communication Engineers
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