抄録
A pipelined analog-to-digital converter (ADC) has been investigated, which has a programmable gain achieved by the gain control in a first-stage multiplying digital-to-analog converter (MDAC). The current consumption reduction under low gain is realized by controlling the transconductance and compensation capacitor of the MDAC circuit according to the input gain. The pipelined ADC designed using a 0.18µm CMOS technology shows a sampling rate of 40MSps and an input gain of 0-18dB (6dB-step). The maximum current consumption is 14.2mA at the input gain of 18dB and the minimum is 7.5mA at 0dB. The signal-to-noise plus distortion ratio (SNDR) is 66.1dB for an input signal amplitude of 2Vpp and an input gain of 0dB, and 63.4dB for an input signal amplitude of 250mVpp and an input gain of 18dB.
