Design and implementation of LT codec architecture with optimized degree distribution

Abstract

In this paper, we present an architecture for ASIC realizations of the Luby Transform (LT) encoder and decoder. To determine the efficiency of the LT Codec architecture, the encoder and decoder are implemented with a core area of 9mm² in TSMC 180-nm 1-poly 6-metal and Samsung 130-nm complementary metal-oxide-semiconductor (CMOS) technology. An empirically modified Robust Soliton degree distribution technique is applied for LT Codec implementation and its performance is analyzed in terms of chip area and cycle count. Instead of including a random generator in the register transfer level (RTL) design, we use different look-up tables (LUTs) for degree distribution, edge routing, addressing and inverse edge routing. Therefore, this architecture is efficient for hardware implementation and occupies less area inside the chip. The result shows that an area of 2.3mm² is required for whole encoder and decoder implementation using TSMC library, of which 0.08mm² is used for encoder implementation. Finally, a modified Robust Soliton degree distribution technique is presented and evaluated in terms of cycle count for different number of iterations using Tensilica tool. Result shows that it takes very less iterations which is more beneficial for hardware implementation of LT Codec.