IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
A low latency semi-systolic multiplier over GF(2m)
Kee-Won KimSeung-Hoon Kim
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2013 Volume 10 Issue 13 Pages 20130354

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Abstract

A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over GF(2m). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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