抄録
A fast-locking fractional-N frequency synthesizer with a fourth-order PLL is presented for a receiver of multiple positioning systems. In order to reduce the locking time a new method of only performing LPF structure transformation is proposed, which exploits the large bandwidth without changing the charge-pump current during the transient state. The bandwidth of the third-order PLL with the second-order LPF during transient state is 10 times larger than that of the fourth-order PLL in the phase-locked state. Furthermore, a pre-charging circuit and the unchanged charge-pump current can significantly accelerate the phase locking. Simulation results show that the longest locking time is less than 10µs in seven modes of three positioning systems (GPS, Galileo and Beidou). For each mode, the in-band and out-of-band phase noises are no larger than -93dBc/Hz and -118.5 dBc/Hz, respectively, and the spurs are less than -56.4dBc at 8.043MHz offset frequency. Total power consumption is 15.21 mW under 1.8V supply.
