Abstract
A low-jitter pulsewidth control loop (PWCL) with high supply noise rejection for high-speed pipelined ADC is presented in this letter. Based on the edge triggered PWCL, An improved charge pump, a novel control stage (CS) and delay compensation circuits (DCC) was utilized to decrease the supply-induced jitter. The experimental results demonstrate that within 180ns the PWCL can lock the clock duty cycles for the accuracy of 50±1% with 10%∼90% input duty cycle from 50MHz to 500MHz. The p-p jitter is 10.1ps at 500MHz, and the variation of duty cycle is less than 0.05% within ±10% supply noise.
