The polarization of radar antenna vary with scan direction. This phenomenon is called Spatial Polarization Characteristic (SPC) of antenna. Based on the SPC of single polarized antenna, a novel polarization estimation method is established. Comparing with the traditional estimation method, this one has the following advantages: (i) It does not need dual-polarization channels to estimate the signal polarization; (ii) The polarization and angle of arriving (AOA) of a periodic signal can be estimated simultaneously; (iii) The full-polarization pattern of the antenna can be matched automatically during the estimation. The feasibility of this method is proved by simulation.

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This paper presents a new method for optimizing the delay of a critical path with an embeded long wire for global routing. And an appropriate effective fan-out factor (EFOF) for optimizing the sizes of the devices in the critical path is derived. Simulations show that the new optimization method can obtain more accurate delay estimation for a critical path than traditional method, which offers significant result for automatic floor-plan and routing in VLSI design.

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Terahertz oscillators using AlAs/InGaAs resonant tunneling diodes with deep and thin quantum wells are reported. Although a thin well has been shown to be effective for high-frequency oscillation until now due to a reduced electron dwell time, it caused an increase in bias voltage. We introduce a deep well with indium-rich InGaAs to maintain or even to reduce the bias voltage. Current-voltage and oscillation characteristics are compared between the quantum wells with 3.5-nm-thick In_0.8Ga_0.2As and 3-nm-thick In_0.9Ga_0.1As. The highest oscillation frequency was 0.96THz for the former while 1.27THz for the latter without increase in bias voltage.

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The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The inter-layer communication is optimized, which facilitates reduction of signal TSVs. What’s more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.

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A compact tunable bandpass filter (BPF) with wide tuning range and improved stopband rejection based on low-temperature co-fired ceramic (LTCC) technique is presented. The axial coupling structure is employed to achieve a wide tuning range and increase resonator Q. To improve the stopband characteristics, Multiple transmission zeros (TZs) are introduced near the passband. A new tunable BPF with a 100% tuning range from 480 to 960MHz has been designed and fabricated to verify the proposed method. The measured results are in good agreement with the electromagnetic (EM) simulation. The circuit only occupies 3.5×3.0×1.7mm³.

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In this paper, we present a photonics-based approach to generating a highly stable coherent terahertz (THz) wave for application to wireless transmission. We introduce a novel system to stabilize the phases of optical carrier signals at different frequencies extracted from an optical frequency comb. By performing an error-free (bit error rate is less than 10⁻¹¹) transmission at 12.5Gbit/s based on amplitude-shift keying modulation and heterodyne detection schemes with a carrier frequency of 100GHz, we were able to verify the importance of phase stabilization.

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Ten resonant wavelengths could be multiplexed successfully by writing long-period gratings (LPGs) with different pitches using a CO₂ laser. A preliminary distributed temperature monitoring experiment was conducted, and it was estimated that separation between 2 adjacent resonant peaks was 13.2nm, even when the temperature difference between 2 adjacent LPGs was 150°C. This separation is large enough to distinguish the resonant wavelengths individually. The results clarified that this multiplexing approach enables the LPFG to detect a local high temperature caused by an abnormal reaction inside large-scale plants.

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In this paper, we propose an improved quad Itoh-Tsujii algorithm to compute multiplicative inverse efficiently on Field-programmable gate-arrays (FPGA) platforms for binary fields generated by irreducible trinomials. Efficiency is obtained by eliminating the precomputation steps required in conventional quad-ITA (QITA) scheme. Experimental results show that the proposed architecture improves the performance on FPGAs compared to existing techniques.

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In this work, a hybrid neural model (HNM) able to characterize accurately the dispersion behavior of the fundamental TE₁₀ mode of a single layer SIW waveguide, is developed. The HNM combines the analytical expression that models the dispersion characteristics of this guiding structure, with a Multi Layer Perceptron Neural Network (MLPNN) which operates as an estimator of the cutoff angular frequency ω_t of the fundamental mode. The comparison among HNM computations, numerical results obtained with methods proposed in literature and full-wave data validate both the accuracy and the effectiveness of the proposed approach.

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A low-jitter pulsewidth control loop (PWCL) with high supply noise rejection for high-speed pipelined ADC is presented in this letter. Based on the edge triggered PWCL, An improved charge pump, a novel control stage (CS) and delay compensation circuits (DCC) was utilized to decrease the supply-induced jitter. The experimental results demonstrate that within 180ns the PWCL can lock the clock duty cycles for the accuracy of 50±1% with 10%∼90% input duty cycle from 50MHz to 500MHz. The p-p jitter is 10.1ps at 500MHz, and the variation of duty cycle is less than 0.05% within ±10% supply noise.

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Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-V_t transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-V_t transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-V_t transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130nm 1P6M Multi-V_t CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.

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This paper presents a new dual asymmetric bit-line sense amplifier to cope with the recent need for GND or VDD bit-line pre-charge scheme for improving bit-line sensing margin and speed of contemporary low-voltage DRAM. The existing GND or VDD bit-line pre-charge schemes have some disadvantages in terms of power, area and practicality, compared to the conventional VDD/2 bit-line pre-charge scheme. Our proposed sense amplifier, which is composed of two asymmetric PMOS sense amplifiers and one symmetric NMOS sense amplifier for GND bit-line pre-charge scheme, and several circuit optimization techniques provide excellent results regarding to stability, speed, and power, while keeping the area overhead under 1% in the size of sense amplifier region. Compared to a conventional VDD/2 scheme, the charge sharing time, sensing time, and pre-charging time have been improved by 20%, 47%, and 20%, respectively and the increase of power consumption due to GND pre-charge scheme has been minimized to 22.2%.

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In this paper, the impact of Si surface roughness on metal oxide semiconductor field effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) sputtering was investigated. The surface roughness of Si substrate was reduced by Ar/4.9%H₂ annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.08nm (as-cleaned: 0.21nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O₂ plasma oxidation. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reduction of Si surface roughness.

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