A new dual asymmetric bit-line sense amplifier for low-voltage dynamic random access memory

Abstract

This paper presents a new dual asymmetric bit-line sense amplifier to cope with the recent need for GND or VDD bit-line pre-charge scheme for improving bit-line sensing margin and speed of contemporary low-voltage DRAM. The existing GND or VDD bit-line pre-charge schemes have some disadvantages in terms of power, area and practicality, compared to the conventional VDD/2 bit-line pre-charge scheme. Our proposed sense amplifier, which is composed of two asymmetric PMOS sense amplifiers and one symmetric NMOS sense amplifier for GND bit-line pre-charge scheme, and several circuit optimization techniques provide excellent results regarding to stability, speed, and power, while keeping the area overhead under 1% in the size of sense amplifier region. Compared to a conventional VDD/2 scheme, the charge sharing time, sensing time, and pre-charging time have been improved by 20%, 47%, and 20%, respectively and the increase of power consumption due to GND pre-charge scheme has been minimized to 22.2%.