Abstract
A novel low power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18µm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10GHz with 1.836mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8GHz with 1.34mW power consumption.
