This letter presents a novel power switch structure using only low threshold voltage MOSFETs to extend the power switch to ultra-low voltage region. The proposed structure deploys series-connected low-Vth footers with two virtual ground ports and selectively chooses the logic cells for connecting to each virtual ground port according to the delay criticality. Moreover, additional circuitries are designed to reduce not only sub-threshold leakage current, but also gate-tunneling leakage and to reduce wake-up time and wake-up fluctuation compared to the conventional power switch. The total power switch size of the proposed power switch structure including the additional circuits is less than the conventional one. The simulation results show that the proposed power gating structure has advantage of low leakage power, small footer size, and low wake-up time, but high-performance, low wake-up fluctuation, wake-up power for inverter chains and ISCAS85 benchmark circuits at 1.1V and 0.6V VDD which are designed using 45nm CMOS technology.
In this letter, a 60GHz tandem coupler using offset broadside-coupled lines is proposed on a silicon-based integrated passive device technology. Over the frequency band of 57-66GHz, the measured insertion loss, amplitude imbalance, input return loss, isolation and phase error of the designed tandem coupler are better than 0.67dB, 0.31dB, 27.9dB, 29.7dB and 3.7° respectively. To the best of our knowledge the proposed coupler achieves the lowest reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate at 60GHz band. Furthermore using the even- and odd-mode analysis, the reason for a high directivity of edge-coupled lines and a low coupling level of broadside-coupled lines on the adopted technology is investigated and a solution for increasing the coupling level of broadside-coupled lines is proposed.
This letter presents a current-shaping technique for static MOS current-mode logic (MCML) prescalers. Simply with two extra current-shaping capacitors the self-oscillating frequecy is increased. A current vector model is also presented to illustrate the principles. The prescaler with the current-shaping technique was fabricated in a 0.18-µm CMOS technology with a reference classic one. The measurement results show that the self-oscillating frequency of the prescaler with current-shaping achieves an improvement of 10%, resulting a 6GHz highest operating frequency while the classic one could only work at 5.3GHz. Consequently, the current-shaping technique improves the maxim divide range of the prescaler with 13.2%.
The low-pass filter (LPF) is a key component for high power RF generators generating 40.68MHz sine wave, since the LPF should reject harmonic noises and handle high input power simultaneously. We propose a novel LPF, operating at 30kW with good skirt performance. The proposed filter is a 7th order Butterworth type and consists of four capacitors and three inductors. The capacitors and inductors are implemented by copper plates, teflon insulators and copper plates with screws, respectively. The measured values of S11, S21 and phase of the proposed LPF are −26.4dB, −0.57dB, and −163.5 degrees at 40.68MHz, respectively. The S21 values at 2nd (81.36MHz) and 3rd (122.04MHz) harmonics are −19.5dB and −29.3dB, respectively. The measured spectrum data on the surface of RF cable that is connected to the LPF output were −41.0dBm at 40.68MHz and −78.8dBm at 81.36MHz. The difference value of 37.8dB is sufficient for harmonic suppression. In addition, arcing and thermal problems do not occur.
In this article a novel feeding system for BST Multiband Antennas is presented. This system is based on a 4×4 Butler matrix that uses a novel triple band hybrid. This hybrid operates on GSM900, DCS1800 and UMTS2100 bands. The presented novel implementation technique in the triple band hybrid can also be used in other application. The Butler matrix network is fabricated on FR4 substrate and the simulated and measured results are presented.
A novel low power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18µm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10GHz with 1.836mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8GHz with 1.34mW power consumption.
In this paper, a highly efficient prototype of Gallium Nitride high electron mobility transistor (GaN HEMT) power amplifier using elliptic low pass filter output network is proposed, fabricated and measured. A fifth-order elliptic low-pass filter network is designed and implemented for the output matching, which provides optimized fundamental and harmonic impedances. Simulation and experimental results show that a Class-E PA is realized from 2.7 to 2.9GHz with 10-W (40dBm) output power, 10dB gain and a measured efficiency of 86%, which is the highest reported today for such a frequency band and output power.