IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A low-power high-speed true single phase clock divide-by-2/3 prescaler
Jianhui WuZixuan WangXincun JiCheng Huang
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JOURNAL FREE ACCESS

2013 Volume 10 Issue 2 Pages 20120913

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Abstract

A novel low power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18µm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10GHz with 1.836mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8GHz with 1.34mW power consumption.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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