IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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An efficient parallel systolic array for AB2 over GF(2m)
Kee-Won KimWon-Jin Lee
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2013 年 10 巻 20 号 p. 20130585

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This paper presents an efficient parallel-in parallel-out systolic array for AB2 over GF(2m) using the polynomial basis. As compared to existing related systolic arrays, the proposed array gains a significant reduction in hardware complexity. The proposed architecture includes the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic architecture for computing an inversion/division operation.
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© 2013 by The Institute of Electronics, Information and Communication Engineers
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