Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors

Abstract

A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2ⁿ sorts of functions at n inputs with different configurations. It only consumes 1 PMOS transistor, 1 NMOS transistor and n SETs, which reduces logic-gate density and power consumption significantly.