IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 20
Showing 1-11 articles out of 11 articles from the selected issue
LETTER
  • Yuan Wang, Baoguang Liu, Wei Su, Junlei Zhao, Xing Zhang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130459
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: July 11, 2013
    JOURNALS FREE ACCESS
    A novel dynamic element matching (DEM) method is presented, called Thermo Data Weighted Average (TDWA) for Nyquist-rate current-steering digital-to-analog converts (DACs). The proposed TDWA encoder technique chooses a sequence of unit current sources and increase or decrease units at different side. Thus this approach can not only reduce the switching number to minimum (as few as thermometer encoder), but also retain good ability to eliminate signal dependent distortions to achieve good linearity at high sampling frequencies.
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  • Jin Woo Jung, Yong Seo Koo, Kwang Yeob Lee
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 20 Pages 20130516
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: September 13, 2013
    JOURNALS FREE ACCESS
    This paper proposes the Low-Dropout regulator including the “load current sensing circuit”. The load current sensing circuit senses the change of the load current and then reduces the ripple of the output voltage. The load transient response characteristic of the Low-Dropout regulator is improved by this method. And this paper uses a body driven technique to enhance the current driving capability for pass transistor. The proposed circuit is simulated by HSPICE with a 0.18μm BCD process parameter. In addition, this paper enhances the reliability of IC by equipping the P-substrate triggered SCR type ESD protection device.
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  • Kee-Won Kim, Won-Jin Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130585
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 02, 2013
    JOURNALS FREE ACCESS
    This paper presents an efficient parallel-in parallel-out systolic array for AB2 over GF(2m) using the polynomial basis. As compared to existing related systolic arrays, the proposed array gains a significant reduction in hardware complexity. The proposed architecture includes the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic architecture for computing an inversion/division operation.
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  • Fengjuan Wang, Zhangming Zhu, Yintang Yang, Xiaoxian Liu, Ruixue Ding
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130666
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 08, 2013
    JOURNALS FREE ACCESS
    Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.
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  • Koichi Maezawa, Jie Pan, Dongpo Wu, Yuichiro Kakutani, Jun Nakano, Mas ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 20 Pages 20130676
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 08, 2013
    JOURNALS FREE ACCESS
    A super regenerative detector employing a resonant tunneling diode (RTD) was investigated for THz wave detection. A key is to use extremely high order harmonics of the fundamental oscillation of the regenerative oscillator. This has various advantages, such as circuit simplicity, easy design, and low power consumption. The basic operation and the possibility of the THz wave detection were demonstrated by circuit simulation.
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  • Ehsan Kargaran, Negar Zoka, Yasser Mafinejad, Abbas Z. Kouzani, Khalil ...
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130690
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 01, 2013
    JOURNALS FREE ACCESS
    An operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) and hybrid compensation technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair. Two separate capacitors are employed for the OTA compensation where one of them is used in a signal path and the other one in a non-signal path. The circuit is designed in the 0.18μm CMOS TSMC technology. The proposed design technique shows remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair OTAs. The Hspice simulation results show that the amplifier has a 92dB open-loop DC gain and a unity gain-bandwidth of 135kHz while operating at 0.4V supply voltage. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical and bio-implantable applications.
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  • Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shice Ni
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 20 Pages 20130697
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: September 24, 2013
    JOURNALS FREE ACCESS
    A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2n sorts of functions at n inputs with different configurations. It only consumes 1 PMOS transistor, 1 NMOS transistor and n SETs, which reduces logic-gate density and power consumption significantly.
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  • Yeong Seob Jeong, Seung Eun Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130699
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 08, 2013
    JOURNALS FREE ACCESS
    Specifically, based on the observation that a response is always preceded by a request in multi-processor SoCs, this letter proposes a novel deadlock-free XY-YX router for on-chip network performance improvement. In order to avoid deadlock, we add additional physical channels in the horizontal direction and optimize the priority of output channel allocation. Simulation results show the enhancement in the throughput of an NoC.
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  • Hiroshi Ishikawa, Tatsushi Nakahara, Hiroki Sugiyama, Ryo Takahashi
    Type: LETTER
    Subject area: Optoelectronics, Lasers and quantum electronics, Ultrafast optics, Silicon photonics, Planar lightwave circuits
    2013 Volume 10 Issue 20 Pages 20130709
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 01, 2013
    JOURNALS FREE ACCESS
    We present a novel parallel-to-serial converter (PSC) that relies on the differential operation of adjacent conversion channels with a common trigger. The new operation scheme clearly improves the device tolerance to the optical trigger pulse energy. The new device is implemented as a compact monolithic optoelectronic integrated circuit (OEIC) on indium phosphide substrate. The device operation is explained and experimentally demonstrated, and the results show good agreement with simulations.
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  • Seung-Il Cho, Seong-Kweon Kim, Tomochika Harada, Michio Yokoyama
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130716
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 09, 2013
    JOURNALS FREE ACCESS
    To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197μW and 58.1μW at 3kHz and 10MHz, respectively.
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  • Ho-yoon Jun, Yong-surk Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 20 Pages 20130743
    Published: October 25, 2013
    Released: October 25, 2013
    [Advance publication] Released: October 08, 2013
    JOURNALS FREE ACCESS
    Single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) code without mis-correction of double non-adjacent error is proposed to achieve high reliability protection against soft errors in on-chip memory systems. To eliminate mis-correction among information bits, the orthogonality of orthogonal Latin square codes is engrafted in the H-matrix of the proposed code. Experimental results show that there is no mis-correction for the proposed code and the overhead of implementation is lower than that of other SEC-DED-DAEC codes. The proposed SEC-DED-DAEC code is suitable for applications to on-chip memory with high reliability.
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