Abstract
Single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) code without mis-correction of double non-adjacent error is proposed to achieve high reliability protection against soft errors in on-chip memory systems. To eliminate mis-correction among information bits, the orthogonality of orthogonal Latin square codes is engrafted in the H-matrix of the proposed code. Experimental results show that there is no mis-correction for the proposed code and the overhead of implementation is lower than that of other SEC-DED-DAEC codes. The proposed SEC-DED-DAEC code is suitable for applications to on-chip memory with high reliability.
