Abstract
This paper presents generalized algorithms for high-throughput parallel scramblers for digital communication circuits. The proposed algorithm can be applied to any three-term scrambler polynomials with the critical path of one register and one XOR gate using the smallest number of registers. The fan-outs of each register can also be determined by calculation. The test chip reveals that the chip area can be reduced by more than 50% compared with that in the literature, and the power dissipation, including the clock buffers, is only 17.33mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps using TSMC 0.18μm CMOS process.
