In this paper the average value between the electric fields, in the ferroelectric layer is assigned to the electric field of the ferroelectric layer. This method reveals good performance for low value of the ferroelectric thicknesses. Furthermore a more precise method is proposed in which the ferroelectric layer is divided into the one region at the gap between the strips and two regions below the strips and constant relative permittivities are assigned to these regions. Applying the method for the structures with different dimensions, approves the accuracy of the method.

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This paper presents a low power, high linearity wideband cascode low noise amplifier (LNA) targeting the multi-standard wireless communication applications including LTE, GSM and Zigbee. Analyzing a cascode amplifier shows the common source (CS) stage is the main nonlinearity source for the LNA. The modified derivative superposition (MDS) technology is widely adopted to improve the linearity. In addition, when the operating frequency increases, the nonlinearity influence coming from the common gate (CG) increases and limits the linearity performance of the LNA. Based on the modified derivative superposition (MDS) technique, this work investigates the nonlinearity effects of the common gate (CG) stage on the cascode amplifier and employs both the derivative superposition (DS) and a terminal LC resonator on the CG stage. The nonlinearity coming from the CG stage is degraded in higher frequency and the high linear bandwidth is also increased. A cascode LNA was designed, analyzed, and implemented in the IBM 0.13-μm CMOS technology. The LNA achieved a third-order intercept point (IIP3) of +13.6dBm, 3dB NF and a 12dB gain in a wide frequency from 700MHz to 1.1GHz.

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This paper presents generalized algorithms for high-throughput parallel scramblers for digital communication circuits. The proposed algorithm can be applied to any three-term scrambler polynomials with the critical path of one register and one XOR gate using the smallest number of registers. The fan-outs of each register can also be determined by calculation. The test chip reveals that the chip area can be reduced by more than 50% compared with that in the literature, and the power dissipation, including the clock buffers, is only 17.33mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps using TSMC 0.18μm CMOS process.

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This paper presents a fully parallelized and scalable RNS Montgomery multiplier over binary field. By generalizing the RNS Montgomery Multiplication (RNS MM) and elaborating a highly efficient RNS base selection, we are able to obtain a considerably high speed in our FPGA implementation experiments with acceptable circuit area and modest critical path delay. Furthermore, this design can be easily scalable by adjusting a variety of field sizes and field polynomials.

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In this letter, we consider the problem of finding sparse signals that share the same support set from their compressed measurements collected at individual sensors in distributed networks, where each sensor has limitations in computational capability and communication power/bandwidth. In order to deal with this problem, we propose a new iterative algorithm which alternates between compressed reconstruction with partially known support at each sensor and adaptive learning support information via cooperative support fusion among sensors. Compared with other existing algorithms, the results obtained by the proposed algorithm show a significant improvement in both noiseless and noisy environments.

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This paper presents a resistance matching based self-testable current-mode R-2R Digital-to-Analog Converter (DAC). The Built-In Self-Test (BIST) circuits are employed to observe the current redistributions in the resistance matching branches converted from the R-2R network in the DAC, and then the redistributed currents are transformed to voltages to detect the R-2R network with extra Design For Testability (DFT) circuits. The circuit-level simulation of the proposed BIST system are presented to demonstrate the feasibility with fault coverage of 96% for R-2R network and 82.6% for the Operational Amplifier (OpAmp), and area overhead of approximately 6%.

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A simple cost-effective LED driver based on the primary-side-regulation (PSR) scheme without auxiliary winding is proposed and designed. The driver operates in discontinuous conduction mode (DCM). By means of controlling the discharging and charging of an internal timing capacitor, the conduction time T_{on_s} of the secondary-side current is monitored and the ratio of T_{on_s} to the switching period T_s is kept constant, resulting in a constant output current. The output current zero cross detecting (ZCD) signal is sensed by the negative change of power MOSFET's source voltage due to the resonance of the primary winding with the parasitic capacitor C_dss of MOSFET. The driving IC and 650V power MOSFET chips are packaged together in SOP-8. The proposed driver is implemented with few external components and its size is minimized. Experimental results show that the current variation is within ±3%, and the efficiency exceeds 80% at the output power of 3-5W under universal input voltage.

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A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 × 20 2D-array is fabricated by 90nm CMOS and 70nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.

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Stacking core layers is emerging as an alternative for future high performance computing, but thermal problems have to be tackled first. When adaptive voltage scaling is adopted to hide the growing variation in the performance of cores, as a result, heat generation of each core varies. By exploiting the static thermal characteristics, the efficiency of dynamic thermal management can be improved. The proposed thermal management reduces the energy consumption by up to 30.02% compared with existing techniques, while keeping the ratio of temperature violations around 1%.

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We have investigated the static and dynamic characteristics of high voltage lateral power diode (L-Diode) on silicon-on-insulator (SOI) substrate with planar / trenched buried oxide (Box) layer on the basis of device simulations. The conduction loss of the conventional L-Diode with planar Box layer is found to be reduced as a result of improving blocking capability by trenching the Box layer. In addition, the switching loss of the conventional L-Diode with planar Box layer, which stems from the second peak of the recovery current, is substantially reduced by adopting the trenched Box layer with suppression of the dynamic avalanche phenomenon.

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Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1s and 0s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

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We propose a multiple-slot silica high-mesa waveguide for infrared sensing considering the possibility of realizing a higher portion of an optical field out of the waveguide (which is defined as “Γ_air”). Low Γ_air leads to less light power being used for sensing, which limits sensing capabilities. The simulated results showed a high Γ_air of 20.3% for a quadruple structure under λ = 1550nm. A scattering loss of 0.06dB/cm was predicted theoretically as well.

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