抄録
This paper presents a new low-power butterfly (BF) unit for single-path delay feedback FFT architectures exploited in multi-path FFT processors. In the proposed BF unit, the power consumption is reduced by replacing multiplexors connected to the outputs of adders in a conventional BF unit with AND gates at the inputs of the adders, which is possible by modifying BF operation. In bypass mode by using the AND gates to set an input of each adder to zero, we can reduce the switching activity in the adders and achieve additional reduction in power consumption. The proposed BF unit synthesized with a 0.13µm CMOS standard cell library achieves an average reduction of 24.8% in power consumption over the conventional BF unit.
