IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A low-offset cascaded time amplifier with reconfigurable inter-stage connection
Kiichi NiitsuNaohiro HarigaiTakahiro J. YamaguchiHaruo Kobayashi
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2014 Volume 11 Issue 10 Pages 20140203

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Abstract

This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a 65-nm CMOS match well with the theoretical estimates and show the effectiveness of this proposed testing structure and reconfigurable inter-stage connection technique.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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