IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 10
Showing 1-13 articles out of 13 articles from the selected issue
REVIEW PAPER
  • Rihito Kuroda, Shigetoshi Sugawa
    Type: REVIEW PAPER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 10 Pages 20142004
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: May 09, 2014
    JOURNALS FREE ACCESS
    Si image sensors with a wide spectral response range and a high robustness to ultraviolet light exposure based on flattened Si surface are described in this paper. A photodiode (PD) fabrication technology is developed to form a thin surface high concentration layer with steep dopant profile on flattened Si surface. Due to this, PDs with a wide spectral response ranging from 200 to 1000 nm is achieved with almost 100% internal quantum efficiency to ultraviolet light (UV-light) waveband. In addition, high robustness of light sensitivity and dark current toward UV-light exposure is obtained. The developed technology is applied to in-pixel buried PDs of photodiode arrays and a CMOS image sensor. The advanced performances of fabricated sensors are verified with experimental results.
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  • Changhwan Shin
    Type: REVIEW PAPER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 10 Pages 20142005
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: May 09, 2014
    JOURNALS FREE ACCESS
    Complementary Metal-Oxide-Semiconductor (CMOS) process and silicon device technologies have progressed dramatically in the last ∼50 years. The achievements of semiconductor industry have dramatically improved the human lifestyle making it smarter. One of the biggest factors in this change is the continued CMOS scaling. However, at sub-30-nm CMOS technology nodes, one of the main technical barriers for reducing the size of CMOS silicon devices is the parametric failure caused by random variations such as line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). This paper discusses these issues in terms of (1) the physical understanding and quantitative evaluation of each random variation source, and (2) the technical solutions to address each of these random variation issues. Lastly, the silicon device scaling scenario from the past, the present and through to the future (i.e., 90 nm technology down to sub-10-nm technology) is briefly discussed.
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LETTER
  • Tomoyuki Uehara, Kohei Hagiwara, Toshihide Tanigaki, Kenichiro Tsuji, ...
    Type: LETTER
    Subject area: Optoelectronics, Lasers and quantum electronics, Ultrafast optics, Silicon photonics, Planar lightwave circuits
    2014 Volume 11 Issue 10 Pages 20140169
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    We propose a novel method to stabilize two external cavity lasers for optical generation of microwave and millimeter wave signals. In our method, two 1550-nm, servo-locked external cavity laser diodes (ECLDs) are simultaneously locked to two resonance frequencies of a single Fabry-Perot optical cavity. The stabilization of two lasers are realized by introducing classical FM sideband technique. In γ-type optical configuration, two wavelengths from the ECLDs with orthogonal polarization are simultaneously phase modulated by a phase modulator with a Faraday rotator mirror. The γ-type optical configuration is designed as a compact, stable and double-pass phase modulation apparatus with same modulation index for two orthogonally polarized signals transmitted through a polarization maintaining fiber. We obtain short-term stability of 200 kHz at an averaging of 10 ms, which is measured with the square root of the Allan variance from the beat note between frequency stabilized lasers.
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  • Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140203
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 17, 2014
    JOURNALS FREE ACCESS
    This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a 65-nm CMOS match well with the theoretical estimates and show the effectiveness of this proposed testing structure and reconfigurable inter-stage connection technique.
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  • Daiki Takeuchi, Wataru Chujo, Shin-ichi Yamamoto, Yahei Koyamada
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 10 Pages 20140209
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: May 02, 2014
    JOURNALS FREE ACCESS
    Two continuous 6-GHz signals were spatially synthesized by two optical beats, so that the microwave power was increased by 6 dB. Time delay difference between two optical beats were adjusted by altering the SMF length or LD wavelength. Also two continuous 20-GHz signals were synthesized by two optical beats and detected by Schottky Barrier Diode. Frequency of the synthesized 20-GHz signal was estimated from the measured time delay difference between two optical beats.
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  • Toru Okazaki, Daisuke Kanemoto, Ramesh Pokharel, Keiji Yoshida, Haruic ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 10 Pages 20140218
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    This paper presents a design method of SAR ADC (Successive Approximation Register Analog-to-Digital Converter ADC) utilizing redundancy bits. In general, binary search algorithm is used as a conventional SAR ADC operation algorithm. It’s possible to realize a high-speed SAR ADC by using non-binary search algorithm which is realized by adding redundancy bits. However, the A/D conversion time varies depending on the number of redundancy bits. Therefore, in order that the conversion time is the shortest, it’s necessary that an appropriate amount of redundancy be added. We show a methodology of finding the appropriate number of redundancy bits.
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  • Dohoon Kim, Hyo Joon Eom, Young Seung Lee
    Type: LETTER
    Subject area: Electromagnetic theory
    2014 Volume 11 Issue 10 Pages 20140219
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    The electrostatic potential in the 3-port pyramidal cell is investigated by solving Laplace’s equation. Potentials are expressed in eigenfunctions in spherical coordinates. The mode-matching method is applied with the orthogonality of sinusoidal function to obtain simultaneous series equations. Numerical computations are carried out to illustrate the behavior of potential and electric field.
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  • Soongyu Kwon, Jong Kang Park, Jong Tae Kim
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140224
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    As the semi-conductor technology advances, the evaluation of soft error hardness for modern electrical and electronic devices becomes more generalized. Related studies have mainly focused on the soft error rate analysis of both combinational and sequential logic circuits, which includes techniques for dynamic simulation, and path-based statistical estimation. In particular, non-dynamic approaches make the entire framework simple and compact. However, when the design under test has a large number of propagation paths, there is still a problem of increasing time complexity. This paper introduces an approximated soft error analysis technique, which constructs lookup tables with which to estimate transient pulses at the primary outputs. The whole process can be finished in polynomial time complexity. We employ node conditional probability to calculate the logical propagation probabilities without using static probability. The experimental results show that compared to the full-path analysis, the approximated technique can speed up the analysis time by 300% while the corresponding error rates for the evaluation results that are obtained are within 16% difference.
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  • Lanhua Xia, Jianhui Wu, Zhikuang Cai, Meng Zhang, Xincun Ji
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140247
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    To ensure qualification of charge-pump locked-loop (CP-PLL), a complete built-in self-test (BIST) scheme should provide functions of measurement of the clock jitter and detection of faults in CP-PLL. This paper proposes a low cost BIST structure providing both the faults detected and timing jitter measured. The structure based on the proposed time-to-digital converter (TDC), which has high resolution and most blocks of TDC are based on the existing blocks in CP-PLL, reduces the test cost and area overhead. The circuit has been designed and simulated in TSMC 0.13 µm CMOS process. The simulation results show that the resolution is about 0.9865 ps and the fault coverage is 98.33%.
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  • Chang-Hyun Bae, Changsik Yoo
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140274
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: May 02, 2014
    JOURNALS FREE ACCESS
    A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-µm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.
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  • Kazunari Minakawa, Kotaro Koike, Neisei Hayashi, Yasuhiro Koike, Yosuk ...
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 10 Pages 20140285
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: May 02, 2014
    JOURNALS FREE ACCESS
    Poly(pentafluorostyrene) (PPFS), which can be easily synthesized and has a low optical loss window at 850 nm, is a promising alternative for a costly perfluorinated polymer as a base material of polymer optical fibers (POFs). To investigate the potential of a PPFS-POF as a Brillouin-based temperature sensing fiber, the Brillouin frequency shift and its temperature dependence of PPFS were measured using an ultrasonic pulse-echo technique. The temperature coefficient, which determines the sensitivity of the temperature sensing, was approximately −7.1 MHz/K independently of the molecular weight and was nearly identical to that in perfluorinated POFs.
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  • Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Ta ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140297
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    Towards a compact and process-variation-tolerant nonvolatile ternary content-addressable memory (TCAM), we propose a novel complementary cell structure with just five transistors and four magnetic tunnel junction (MTJ) devices (5T-4MTJ). The complementary cell structure enlarges output voltage swing of each cell circuit together with match-line voltage swing in word circuit constructed by many bits of cell circuits, which eliminates search errors. We also propose a novel bit-parallel writing scheme, called phase-selective parallel writing, for the cell circuit. Every data is written into a complementary MTJ-device pair in two phases by selectively asserting bit-lines during 0-write phase or 1-write phase, not directly assigning write data to the bit-lines. Consequently, the phase-selective parallel writing scheme enables four-phase write for the proposed 5T-4MTJ-based word circuit.
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  • Zhengmin Zhang, Lin Zhang, Zhenqiu Ning, Xing Jin
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 10 Pages 20140307
    Published: 2014
    Released: May 25, 2014
    [Advance publication] Released: April 25, 2014
    JOURNALS FREE ACCESS
    To provide a high EMI resisting Local Interconnection Network (LIN) transmitter, a novel structure with an error feedback amplifier composed of low input impedance transconductance amplifier was proposed. The circuit was fabricated in 0.5 µm 60 V BCD process and was simulated hiring the standard IEC62132-4: Direct Power Injection (DPI) method. Simulation result showed that the performance of the duty cycle satisfied the requirement under the condition of superimposing more than 5 W Electromagnetic interference (EMI) ranged from 150 KHz to 1 GHz onto LIN bus.
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