A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding

Abstract

This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAI-ADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-µm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498 MHz input frequency at the rate of 1.0 GS/s. The power consumption is 98 mW with sampling rate of 1.0 GS/s and supply voltage of 1.2/2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step.