Although flip-chip transitions have smaller parasitics than bonding wires, they should be carefully designed at 60 GHz. Insertion loss at a flip-chip transition may differ as much as 2 dB depending on design parameters. In this paper we present a comprehensive sensitivity analysis to optimize the flip-chip transition.

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In this paper, an ultra-wideband, ultra-fast, fine resolution and compact digital instantaneous frequency measurement (DIFM) is proposed. The algorithm is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. Due to only one high speed comparator with some relative circuits are needed, this DIFM can be blended in other digital system with compact size. The RocetIO GTP has been successfully introduced in this system for the interface with comparator. Thanks to the advantage of 1.46 GHz wide-band, the large numbers of RF channels required in traditional solutions can be decreased. Comparing to traditional analog and digital method, this design is more flexible to reconfigure, easy to adjust, and with smaller size. The measurement results show that our invention is capable of detecting short wave pulse and continuous wave (CW) signal from DC to 1.46 GHz with a major error within 1.25 MHz in less than 200 ns throughput time. This digital instantaneous frequency measurement (DIFM) system has been successfully used in radar systems.

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A multistatic high-frequency (HF) ocean radar is proposed that could be used both for surface current mapping and ship tracking. Through fine tuning the carrier frequency of the transmitting signals, echoes produced by different transmitters could be separated in the baseband. Shore-based Automatic Identification Systems (AIS) are used for receiving antenna calibration and ship tracking result verification. A two-month experiment was conducted on the coast of the North China Sea from October to December in 2013. The primary data processing results prove the effectiveness of the radar system.

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It is known that when the cylindrical wave propagates from a positive index material (PIM) to a negative index material (NIM), the backward lateral wave is excited along the interface between the PIM and the NIM over a half-space metamaterial. In this study, by using the saddle point technique, we shall derive a novel high-frequency uniform asymptotic solution for the reflected and scattered fields over a half-space metamaterial with the NIM. The validity and utility of the novel uniform asymptotic solution is confirmed by comparing with the reference solution calculated by the numerical integration of the integral representation for the reflected and scattered fields. We have also shown the physical interpretation of the uniform asymptotic solution.

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This study performs analytical investigation of how accurately three existing phase shift models describe the phase shift impulse response of a simple planar oscillator. The investigation finds that Kaertner’s model perfectly describes the behavior of the phase shift impulse response, whereas the projection-based ISF, and the perturbation projection-based model oversimplify it to its initial, and final state, respectively. These findings are supported by the simulations of the phase shift impulse response of the planar oscillator. Additionally, the simulations of phase shift impulse train response reveal that only Kaertner’s model can closely follow the time evolution of the phase shift impulse train response.

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A closed-loop sigma-delta (ΣΔ) capacitive microaccelerometer interface circuit is proposed in this work based on the time shared multiplexing electrostatic feedback and correlated-double-sampling (CDS) techniques. The noise analysis of the proposed low noise capacitance detection circuit is presented. The interface circuit is fabricated in a standard CMOS process and the active area is 13 mm². The chip consumes 20 mW from a 5 V supply and the sampling frequency is 250 kHz. The measured results show that the sensor achieves a noise floor of 6 µg/Hz^1/2 in a closed-loop operation over a 1.5 kHz bandwidth, and the achieved figure of merit (FOM, 53 pW/Hz) is better than the previously reported ΣΔ interfaces.

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A fifth-order fully differential interface circuit (IC) with on-chip-test function is presented to improve the noise performance for micromechanical sigma-delta (Σ-Δ) accelerometer. The proposed on-chip-test technique for Σ-Δ accelerometers avoids a shaker table applying a sinusoidal signal as the simulated acceleration which involves distortion itself. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in a larger dynamic range (DR). The post-simulation results show that the electrostatic force feedback linearization circuit decreases the harmonic distortion effectively and the proposed on-chip-test technique achieves 98 dB third-order harmonic distortion detection, and the nonlinearity of the proposed circuit is 0.02%.

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A digital background calibration technique that compensates for capacitor mismatches is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in the SAR ADC based on tri-level switching. The termination capacitor in the digital-to-analog converter is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation result shows that the signal-to-noise and distortion ratio is improved from 57.1 dB to 72.0 dB and the spurious free dynamic range is improved from 62.0 dB to 82.6 dB.

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A low-distortion bandpass (BP) sigma-delta (ΣΔ) modulator with double-sampling technique is proposed. The proposed modulator is based on a double-delay switched-capacitor resonator which employs double-sampling technique to relax the requirements for circuits and reduce amplifier power consumption and chip area. The proposed architecture can be applied for other modulators. The full differential circuit using two-path technique is designed with a standard 0.18 µm CMOS technology. The power consumption is 6 mW with 1.8 V supply. The fourth-order single-bit BP modulator achieves a peak SNR (signal-to-noise ratio) of 86.6 dB and DR (dynamic range) of 90 dB with 200 kHz bandwidth centered at 20 MHz which are better than the conventional BP ΣΔ modulator.

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Asymmetric monotonic switching scheme is proposed for a low power successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed switching procedure consumes no energy from reference voltage for the first 3 MSB (most significant bit) conversion using unequal initial DAC setting and asymmetric binary search algorithm. After 3 MSB conversions, DAC switching utilizes a conventional monotonic DAC switching for further energy saving. As a result, average energy saving during conversion cycles has been improved up to 98.5% as compared with conventional architectures.

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This paper reports systematic appraisal of wavelet transform based de-noising receiver, for high speed indoor optical wireless communication. For upcoming high speed indoor optical wireless communication systems, wavelet transform based de-noising receiver in indoor environment represent grand consideration. Performance evaluation is carried out in the presence of natural (sunlight) and artificial light sources (incandescent light) in typical room environment. The performance of receiver is considered in two arrangements: They are single channel imaging receiver (SCIR) and wavelet transform based de-noising receiver. The second scheme provides better results than first scheme (SCIR). The simulation results for both SCIR and wavelet transform based de-noising receiver are shown. The simulation results indicate that the wavelet packet transform (WPT) based de-noising receiver offers increased received optical power, signal to noise ratio (SNR), and reduced bit error rate (BER), path loss compared to the SCIR and discrete wavelet transform based de-noising receiver.

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This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAI-ADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-µm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498 MHz input frequency at the rate of 1.0 GS/s. The power consumption is 98 mW with sampling rate of 1.0 GS/s and supply voltage of 1.2/2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step.

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This paper proposes a loop prediction encoding method for decreasing power consumption on instruction memory address bus. The loop prediction encoding is based on detecting and predicting loop programs. The experiment results show that our method can decrease switching activity up to 81.5% on average, with small overheads on performance and area.

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Millimeter-wave (MMW) signal generation devices using difference frequency generation (DFG) based on the second order nonlinear optical effect in a rectangular waveguide were studied in detail theoretically and experimentally. The temporal and spatial coupling process of a generated MMW signal to a TE₁₀ mode in a rectangular waveguide embedded with a nonlinear crystal was analyzed using the finite-difference time-domain (FDTD) method. In the experiment, 60 GHz-band signals were successfully obtained from fabricated proto-type devices using a rectangular waveguide embedded with z-cut LiTaO₃ crystal.

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A new CMOS bandgap voltage reference (BGR) is proposed and simulated using Silterra 0.13 µm CMOS technology. The proposed BGR utilizes 3 curvature-corrected current generators that compensate for the output voltage variation in an extended temperature range. The proposed circuit generates an output voltage of 1.181 V with a variation of 380 µV from −50 °C to 150 °C.

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A simple scheme for rail to rail op-amp operation is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. It uses very compact control circuitry. Experimental verification is provided from a test chip prototype in 0.5 µm CMOS technology.

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A semi-distributed step attenuator with low insertion loss and low phase distortion is presented with 0.18 µm BiCMOS process, which is implemented with a step distributed attenuator for 0–7 dB attenuation with low insertion loss and two π-type switched resistive attenuation modules for large attenuation amplitude. The proposed attenuator has a maximum attenuation range of 0–31 dB with 1 dB-increase at the frequency range of 10–20 GHz and involves less than 8.6 dB of insertion loss. The RMS amplitude error and insertion phase at each attenuation state are less than 0.6 dB and 3°, respectively.

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A novel solid state drive (SSD) controller integrated circuit structure is presented. This controller has up to five flash memory channels. These five channels, regarded as four independent virtual disks in a redundant array of independent disks (RAID) system, can be configured as RAID0 or RAID5 mode. This real silicon controller was silicon proven working well in a single SSD unit with intrinsic RAID (iRAID) functions configured as either RAID0 or RAID5 mode. The traditional concept that RAID has to be built up by multiple independent disks has been changed by this single SSD unit with intrinsic RAID embedded. It brings a new way to make big RAID storage systems at lower costs, higher performances, less power consumption, smaller in size and easier maintenance.

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In this paper, a low power RSSI architecture with low voltage supply is proposed, in which an improved BJT based feedback logarithmic amplifier is raised. Besides, temperature drift and process variation are considered. This approach is verified in TSMC 0.13 µm CMOS process. With a 1.2 V supply, the proposed RSSI consumes 200 µA and provides 50 dB linear range with less than 2 dB error.

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In this letter a novel lateral insulated gate bipolar transistor with a three dimensional (3D) bypass anode design on silicon-on-insulator (SOI) is proposed and discussed. The 3D bypass anode concept makes it more effectively not only suppress the snapback effect in conducting state, but also improve the switching speed as a fast electron extraction path during turnoff without wasting the anode area. Numerical simulation results show that the proposed LIGBT structure has a 1.12 V forward voltage drop and 400 ns turnoff time at current density of 100 A/cm². The proposed LIGBT saves the cell area by above 30% compared with the conventional no snapback SA-LIGBT and has about 61% reduction in turnoff time compared with the conventional LIGBT, respectively. Mostly, the proposed LIGBT can be fabricated by the conventional SOI smart power IC process without an additional process step and mask.

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