A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

抄録

A nonvolatile flip-flop (NV-FF) is proposed for a zero-standby-power LSI using a domain-wall motion (DWM) device. Since the write current path is separated from the read current path in the DWM device, two nonvolatile memory function blocks, a write driver for storing temporal data into the DWM device, and a sense amplifier for recalling the stored data from the DWM device can be optimized independently. Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge them into a CMOS delay flip-flop (D-FF) core. Since the nonvolatile storage cell is electrically separated from the D-FF core during the normal operation, there is no performance degradation. In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.