LETTER
A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell
2014 年 11 巻 13 号 p. 20140396
詳細
2014 年 11 巻 13 号 p. 20140396
A novel layout structure for the typical 6T-SRAM cell is designed to mitigate the single-event induced MBU. And three-dimensional technology computer-aided design (TCAD) numerical simulation is used to evaluate the MBU hardening performance of this novel layout structure. Compared to other layout structures, our proposed layout can effectively attenuate the single-event induced MBU in typical 6T-SRAM with little area and power penalty.
