Digital nonlinearity calibration for pipelined ADCs using sampling capacitors splitting

Abstract

A digital background calibration method correcting nonlinear errors of residue amplifiers in pipelined ADCs is presented. The technique makes use of the proportional scaling feature of linear systems to measure and correct severe nonlinearity errors, and is highly effective once there is a non-zero input to the ADC, regardless of the input distribution. Simulation shows that using the proposed digital calibration, SNDR is improved from 58 dB to 91 dB and SFDR from 68 dB to 104 dB, in a 16 bit prototype pipelined ADC with 1% capacitor mismatches and a residue amplifier having up to 10.3% gain compression in the 1^st pipeline stage.