IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 13
Showing 1-22 articles out of 22 articles from the selected issue
LETTER
  • Chunzao Wang, Bin Zhang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140294
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    A novel insulated gate bipolar transistor (IGBT) entitled NPN aided fast switching IGBT (NFS-IGBT) with a P-buffer layer is presented, which enhances the switching speed greatly. Compared with the conventional IGBT, double sided NPN structure is incorporated into the anode to facilitate the turn-off process. The proposed structure is verified by two-dimensional mixed device-circuit simulation, which indicates that the turn-off time is drastically reduced to one third of the conventional value at the expense of acceptable increase of on-state voltage drop. The tradeoff performance also shows great improvement for the new structure.
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  • Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tad ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140296
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    A nonvolatile flip-flop (NV-FF) is proposed for a zero-standby-power LSI using a domain-wall motion (DWM) device. Since the write current path is separated from the read current path in the DWM device, two nonvolatile memory function blocks, a write driver for storing temporal data into the DWM device, and a sense amplifier for recalling the stored data from the DWM device can be optimized independently. Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge them into a CMOS delay flip-flop (D-FF) core. Since the nonvolatile storage cell is electrically separated from the D-FF core during the normal operation, there is no performance degradation. In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.
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  • Jun Dong, Yihong Zhou, Tao Yang, Haiyan Jin
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140316
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    A compact waveguide-to-half mode substrate integrated waveguide (HMSIW) transition using antisymmetric tapered probes is proposed. A good matching of field and impendence is achieved by the tapered probes. To verify the proposed transition, a back-to-back test module at Ka-band is fabricated and measured. It provides a return loss better than 14 dB and an insertion loss of 0.35 to 1 dB within a frequency range from 25 to 40 GHz. There is no need of intermediate transition for this design. The size of the proposed transition is reduced by approximately 83.8% as compared with the waveguide-to-HMSIW transition using antipodal fin-line.
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  • Ping Huang, Hui Wang, Cheng Yang
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140318
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    In this paper, a novel non circular ROOTMUSIC algorithm for direction of arrival (DOA) estimation in monostatic MIMO radar is proposed. The properties of noncircular signals can be used to form a new virtual array, which enhances the angular resolution. Then a reduce-dimensional transformation matrix is designed to convert the received data into a lower dimensional space, and the DOAs can be obtained by Root-MUSIC algorithm. Compared with RD-ESPRIT method and Root-MUSIC algorithm, the proposed method has better angle estimation performance and handles more targets than RD-ESPRIT. Simulation results are presented to verify the effectiveness of the proposed algorithm.
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  • Tsuyoshi Funaki
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140350
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    SiC power devices generally operate with fast switching. The fast switching operation in power conversion circuits suffer from the self turn-on phenomenon of a power MOSFET in which the gate voltage is induced to fluctuate by the turn-on operation of the MOSFET on the other side in the bridge circuit. The self turn-on results in a large power loss, when the fluctuating gate voltage exceeds the threshold gate voltage. This paper analytically discusses the self turn-on phenomenon of the MOSFET related to the turn-off operation of its body diode, which is initiated by the turn-on operation of the MOSFET on the other side in the bridge. This analysis was evaluated experimentally.
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  • Arun Ambashanker, Palanisamy Nirmal Kumar
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140352
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    The shortcoming of conventional bus architecture has been overcome by adopting Network on Chip (NoC) in multi core System on Chip (SoC). Many works have been anticipated for NoC, based on network topology, switching methodology and routing techniques. This paper proposes a Modified TACIT algorithm for secure routing in NoC architectures. The key generation is based on four types of HASH function (4H-key) that find hard hitting to the intruder. The algorithm is realized under various block sizes as the 8-bit, 64-bit and 128-bit. The device utilization of the proposed algorithm is determined and the results show that, the maximum frequency achieved by the proposed algorithm (for 8-bit block size) is 640.968 MHz with the total memory usage of 78045 Kb.
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  • Jongsu Park, Heejun Yun, Sangook Moon
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140357
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    We propose a scheme for enhancing the MPI (Message Passing Interface) broadcast function performance with supporting hardware logic to reduce a number of synchronization processes which can be avoided on a distributed memory multiprocessor system on a chip (MPSoC). We accomplish this using the concept of atomic execution which facilitates full pipeline utilization. To validate our approach, we implemented a bus functional model with systemC and evaluated the results against various message data sizes and number of nodes. Evaluation results showed that performance improvement can be achieved by up to 230% over the precedent pipelined message broadcast method. Synthesis results with 4 processing nodes show that the extra hardware cost for the proposed atomic pipelined broadcast logic occupies only 2.4% of the entire area.
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  • Sangkwon Lee, Jinseong Jeong
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140385
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    In this paper, a boost converter with fast MPPT capability is proposed for energy harvesting applications. The sampling time for maximum power point voltage, VMPP of harvester device is extremely shortened by using inductor current conservation method and an off-chip input capacitor-less boost converter. The proposed boost converter is designed in a standard 0.13 µm CMOS process and compared with a conventional MPPT boost converter. The proposed architecture can sample VMPP more than 100 times faster than the conventional architecture. Power conversion efficiency of the harvesting system also improves due to the fast VMPP sampling. For the scenario used in this paper, the overall efficiency improves from 70% to 85%. This architecture can be applied to any energy harvesting systems and is especially effective when the ambient parameter such as temperature or light intensity changes relatively rapidly.
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  • Xu Hui, Zeng Yun
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140396
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    A novel layout structure for the typical 6T-SRAM cell is designed to mitigate the single-event induced MBU. And three-dimensional technology computer-aided design (TCAD) numerical simulation is used to evaluate the MBU hardening performance of this novel layout structure. Compared to other layout structures, our proposed layout can effectively attenuate the single-event induced MBU in typical 6T-SRAM with little area and power penalty.
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  • Hyunpil Kim, Sangook Moon, Yongsurk Lee
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140407
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    In this study, we propose a radix-16 Booth multiplier using a novel weighted 2-stage Booth algorithm. Most conventional multipliers utilize radix-4 Booth encoding because a higher radix increases encoder complexity. To resolve this problem, we propose the weighted 2-stage Booth algorithm. The synthesis results show that the multiplier using the proposed algorithm achieves better power-delay products than those achieved by conventional Booth multipliers. We believe that the proposed Booth algorithm can be broadly utilized in general processors as well as digital signal processors, mobile application processors, and various arithmetic units that use Booth encoding.
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  • Jong-Phil Hong
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140428
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    This paper presents a gm-boosted differential Colpitts VCO with a switched capacitor tuning scheme which achieves low phase noise and a wide tuning range at a low supply voltage. In the proposed VCO, a voltage boosting circuit increases a turn-on resistance of the switching transistor for the capacitor array by generating higher gate bias voltage. As a result, the proposed VCO can achieve a wide frequency tuning range at a low supply voltage. The proposed VCO is implemented with 0.18-µm CMOS technology and oscillates from 3.60 to 4.14 GHz. Measurement results indicate a phase noise of −123.65 dBc/Hz at 1-MHz offset at 3.63 GHz, while dissipating 2.53 mA from the 0.7-V supply.
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  • Teng Li, Hongfu Meng, Wenbin Dou
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140434
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    A broadband transition between substrate integrated waveguide (SIW) and rectangular waveguide (RWG) is proposed. Five ridged steps in the RWG and a multi-section SIW are designed to expand the bandwidth. The measured results agree well with the simulations, a return loss better than 15 dB and an insertion loss less than 2.45 dB are obtained at the wide band from 23.83 GHz to 40 GHz for a back-to-back structure.
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  • Fan Chaojie, Lu Yuxiao, Wang Ke, Zhou Jianjun
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140442
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    A digital background calibration method correcting nonlinear errors of residue amplifiers in pipelined ADCs is presented. The technique makes use of the proportional scaling feature of linear systems to measure and correct severe nonlinearity errors, and is highly effective once there is a non-zero input to the ADC, regardless of the input distribution. Simulation shows that using the proposed digital calibration, SNDR is improved from 58 dB to 91 dB and SFDR from 68 dB to 104 dB, in a 16 bit prototype pipelined ADC with 1% capacitor mismatches and a residue amplifier having up to 10.3% gain compression in the 1st pipeline stage.
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  • Takashi Ohira
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140448
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    This paper describes how the port voltage and current vectors behave in linear two-port power transfer systems. We find there is an optimum set of them at which the output power reaches its highest while keeping the input power constant or vice versa. Derived maximum available efficiency formulas work with a power source having any impedance e.g. zero- or infinite-ohm. Heuristically discovered angle parameter θ enables us to graphically predict the system’s maximum available efficiency from its port parameters i.e. matrix Y, Z, or S in 50-ohm domain.
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  • Eduardo Ortega-Torres, Sergio Ruíz-Hernández, Carlos Sánchez-López
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140467
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 26, 2014
    JOURNALS FREE ACCESS
    In this letter, the nonlinear behavioral model of a third-order chaotic system based on CFOAs is introduced. The proposed model is more realistic than PWL approaches widely used in the literature, since herein real physical active device performance parameters along with its parasitic elements are taken into account in the modeling process. As a consequence, chaotic attractors at 1-D can not only be better forecasted, but since chaotic waveforms numerically and experimentally generated have a random behavior, statistical tests are used to measure the similitude between them. Experimental results of the chaotic system designed with the AD844AN integrated circuit are gathered, showing good agreement with theoretical simulations.
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  • Dyukyoung Moon, Hyunseul Lee, Changhwan Shin, Hyungcheol Shin
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140468
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 12, 2014
    JOURNALS FREE ACCESS
    The characteristics of the Random Telegraph Noise (RTN) in Gate-Induced Drain Leakage (GIDL) current are first investigated. Based on the Hurkx model, a new model is developed for the Trap-Assisted-Tunneling (TAT) and Band-to-Band Tunneling (BBT) regimes in Saddle Metal-Oxide-Semiconductor Field-Effect Transistor (Saddle MOSFET) for DRAM applications. The three-dimensional Technology-based Computer Aided Design (TCAD) simulator is used to quantitatively analyze and model the RTN. The RTN amplitude in GIDL current (i.e., ΔI/I) increases with increasing drain-to-gate voltage (VDG) in the TAT regime, whereas ΔI/I decreases with increasing VDG in the BBT regime. Simulation results are well matched to the results estimated by the newly-proposed equations derived from the Hurkx model. This model would open a new pathway for the RTN analysis in DRAM devices.
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  • Hua-Pin Chen, San-Fu Wang, Ming-Yuan Hsieh
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 13 Pages 20140478
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    A novel tunable current-mode and voltage-mode quadrature oscillator design using a single differential voltage current conveyor transconductance amplifier (DVCCTA) and four all grounded passive elements is presented. The proposed circuit offers two explicit quadrature current outputs and two quadrature voltage outputs. The oscillation condition and oscillation frequency of the proposed oscillator are independently controllable. The use of only grounded passive components makes the proposed circuit ideal for integrated circuit implementation. HSPICE simulation results are given to verify the theoretical analysis.
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  • Dong Wang, Peng Cao, Yang Xiao
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140481
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 26, 2014
    JOURNALS FREE ACCESS
    Constant correction truncated multiplier can minimize hardware cost and power dissipation by computing only the most significant bits of partial products. However, traditional schemes introduce large truncation errors that degenerate the accuracy of the target application. In this brief, we propose an improved scheme that can significantly reduce such truncation errors. The proposed scheme estimates an accurate compensating constant by correctly counting the probability of occurrence of the input operand and the product bits with a group of probability propagation formulas. The proposed truncated multiplier is coded in Verilog RTL, implemented in 65 nm standard cell technology, and applied in image compression and color space conversion applications. Experimental results show that our scheme achieves an average peak signal-to-noise ratio (PSNR) improvement of 4.09 dB and 2.31 dB over state-of-the-art truncation scheme in the two applications, respectively. When the same truncation error range is desired, the proposed scheme can save around 5.8% of circuit area.
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  • Song Xin-wu, Lin Jian-hui
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140485
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    In order to solve the problem that power supply of the sensor in a certain type of acceleration monitor fails under the 2 kV level of EFT test, this article aims to design an optimized EFT filter based on the current typical one. In fact, the insertion loss and output voltage are both calculated by equivalent circuit. According to the comparison between the new filter and the typical one, it can be concluded that the optimized filter tends to function with better performances and efficiency, which can be confirmed by the EFT test.
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  • Eunji Lee, Kern Koh, Hyokyung Bahn
    Type: LETTER
    Subject area: Storage technology
    2014 Volume 11 Issue 13 Pages 20140520
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 19, 2014
    JOURNALS FREE ACCESS
    This letter analyzes the characteristics of write operations in file systems for PCM (phase-change memory), and observes that a large proportion of writes only involve a small modification of the previous version. This observation motivates a new file system for PCM called P2FS, which reduces write traffic to PCM by exploiting the similarity of data between versions, while preserving the same reliability level of existing copy-on-write file systems. Experimental results show that P2FS reduces file I/O time by 48%, and energy consumption by 65%, on average, compared to copy-on-write.
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  • Lingyan Fan, Jianjun Luo, Hailuan Liu, Xuan Geng
    Type: LETTER
    Subject area: Storage technology
    2014 Volume 11 Issue 13 Pages 20140535
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 26, 2014
    JOURNALS FREE ACCESS
    AES has been one of the most popular encryption and decryption algorithms for data security applications. At the same time, data randomization (or “homogeneous”) technology was applied to reduce the bit error rate (BER) of MLC and TLC flash memory. Here, AES algorithm was found efficient to replace the orthogonal polynomials which normally carry out homogeneous function by scrambling data. This paper put forward a novel hardware architecture providing both homogeneous and data encryption/decryption functions concurrently by an embedded AES hardware engine while getting rid of randomization engine with Linear Feedback Shift Register (LFSR). It made a flash controller simple and reduced the die size because the independent homogeneous hard engine is no longer necessary for a flash memory system, in which AES security algorithm embedded. Finally a SSD controller designed in this architecture was silicon proven.
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  • HongKyun Lym, HwanSool Oh, JaeEun Pi, Chi-Sung Hwang, SangHee Ko Park, ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 13 Pages 20140539
    Published: 2014
    Released: July 10, 2014
    [Advance publication] Released: June 26, 2014
    JOURNALS FREE ACCESS
    A 5 V input level shifter circuit based on depletion-mode In-Ga-Zn-O thin-film transistors (TFT) worked up to 100 kHz. By employing metal-insulator-semiconductor (MIS) active capacitor, we enhanced the bootstrapping effect and reduced the rise time of the output signal. SPICE simulation results showed that the proposed level shifter worked for wide threshold voltage range from −2 V to +1 V and the fabricated circuit exhibited the propagation delay tplh and tphl of 0.6 µsec and 0.3 µsec respectively.
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