抄録
In this express, we propose Booth encoding high-speed modulo (2n − 2p − 1) multipliers on the condition length of (Cout) ≤ min(2n − p, n + p), where Cout is the carry-out output of the carry save adder tree that is used to compress the partial products and the correction term after splitting, shifting and resetting. Synthesized results demonstrate that the proposed Booth encoding modulo (2n − 2p − 1) multipliers have a good delay performance.
