This paper presents a transpose-free variable-size fast fourier transform (FFT) accelerator on a digital signal processing (DSP) chip. Several parallel schemes are utilized to calculate a batch of small-size FFT algorithms to achieve high performance and throughput. For middle- and large-size of FFT, we propose a transpose-free Cooley-Tukey scheme that uses the random access feature of on-chip SRAM memory to avoid the DDR access of matrix with column-wise and improves the utilization of DDR bandwidth. Experimental results show that our FFT accelerator, implemented with 65 mn library and run at 500 MHz, can achieve the energy efficiency improvement by two orders of magnitude compared with Intel Xeon CPU and obtain above 50× performance improvement compared with TI TMS320C64X DSP chip.

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Signal integrity perturbations are unavoidable in current high performance circuits implemented in nanometer technologies. In this paper, a novel methodology based on the signal addition of two digital signals to verify skew violations is proposed. This methodology allows the implementation of a compact sensor for on-chip verification of the skew in digital interconnect signals. The monitor is implemented in a commercial CMOS 65 nm technology. The compact size of the monitor allows its use for verifying several internal nodes with low area penalty. The impact of process, power supply voltage and temperature variations (PVT) on monitor resolution is analyzed. Simulation results show that the monitor is effective for identifying abnormal skews due to signal integrity issues.

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We propose a digital wideband receiver scheme covering multiple Nyquist zones by exploiting phase and magnitude mismatch in the conversion from real-valued signals to complex-valued signals. The digital wideband receiver is designed to detect uncooperative signals. The magnitude/phase mismatch due to an imperfect hybrid coupler is often considered undesirable and needs to be compensated. However, by exploiting the frequency-dependent magnitude/phase mismatch phenomenon, we can distinguish signals from different Nyquist zones. Simulation results demonstrate that, using carefully designed magnitude/phase mismatch, we can detect signals over multiple Nyquist zones. The proposed method can lead to a new wideband receiver design.

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The range alignment approach is applied to solve the misalignment between the sampling clock and trigger pulse for signal acquisition system of pulse and Doppler (PD) radar. Adjacent pulse correlation (APC) and minimum entropy (ME) methods are utilized to suppress sidelobes and promote the detection performance. Experimental results have demonstrated the effectiveness of proposed methods.

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This paper reports a reconfigurable patch antenna using a novel dual-slit perturbation for circular polarization diversity. The proposed antenna consists of the dual-slit with in- and out-slit at a diagonal corner and three identical single-slits at the residual corners for generating right- and left-handed circular polarization. By controlling two pin diodes mounted in the dual-slit, the size of the slit can be switched and circular polarization diversity can be achieved. The measured results of the implemented antenna which employed the dual-slit show a good agreement with the simulation results and demonstrate an excellent controllability of alternating circular polarization senses at the resonant frequencies.

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This paper proposes a simple and cost-effective configuration for an analogue Radio on Fiber (RoF) link without any amplifier comprising driver and receiver circuits with stubbed microstrip lines. This simple configuration yields a gain of +4 dB with a spurious free dynamic range (SFDR) of 58 dB. An adjacent carrier leakage ratio (ACLR) of less than −63 dB and an error vector magnitude (EVM) of less than 1% are also achieved. These results satisfy the specifications given in the technical standard published by the third generation partnership (3GPP).

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To remove the noise folding effect, which is a primary cause of degradation of the close-in phase noise of fractional-N phase-locked loops (PLLs) that use sigma-delta modulation, a fractional-N frequency synthesizer for broad-band and multi-standard mobile TV tuners was designed. The proposed skewed-reset phase frequency detector (SR-PFD) provides a key solution to the problem of noise folding by enhancing the linearity of the phase frequency detection path through the charge pump (CP). Degradation of the reference spur —the unwanted effect in SR-PFDs— is blocked through the use of a sampled loop filter. An SR-PFD in a frequency synthesizer fabricated on a 180 nm CMOS process enhanced phase noise by 10 dB or more by using a multi stage noise shaper (MASH) 1-1-1 sigma-delta modulator (SDM), while a sampled loop filter decreased the amplitude of the reference spur by 7–13 dB.

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A method for optimizing the read/write current on phase change memory array is proposed. A smart current adjustment circuit is designed to bi-directionally alter the internal read/write current. The best read/write condition based on arrays can be found through this adjustment approach. Example of a 2-dimensional shmoo test on a 16k-bit phase change array implemented in 0.13 µm CMOS technology is given. The resistance distribution can also be roughly obtained. This method, taking advantage of the peripheral circuit, provides statistical yield data on a variety of read/write current, thus offering reliable and helpful indicators for chip parameter setup and process optimization.

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An asymmetric Mach-Zehnder interferometer optical switch using phase-change material (PCM) is reported. In this switch, two Ge₂Sb₂Te₅ thin films, each 1 µm in diameter, are deposited on a Si waveguide, and are used as phase shifters. The PCM can be reversibly switched between the amorphous and crystalline states. The difference in refractive index between the two states is very large, typically more than 2. Therefore, an optical switch using the PCM can be very small. The switching operation is successfully demonstrated by laser pulse irradiation. The maximum extinction ratio is 26.7 dB, and 2.2-nm peak wavelength shift is verified.

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A “roofline model” is a system performance and optimization guide for programmers and system engineers to apply in the design of future architectures. We review a conventional roofline model and propose a working set size (WSS)-based roofline model. Because of the recent increase in the performance of embedded systems, we investigated embedded systems based on an ARM architecture. Our proposed scheme presents practical guidelines for a multi-core architecture when the program uses a small WSS.

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We demonstrate a 100 Gbit/s real-time digital coherent transmission over a 32-km multi-mode graded-index fiber (GIF) with a 62.5 µm core diameter by compensating for modal dispersion with a digital signal processing (DSP). The DSP enables channel estimation and configuration as fast as 20 ms. Furthermore, the optical channel can be switched between GIF and a single-mode fiber (SMF) within 30 ms.

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When a pulse transmits through delay stages, it dies out after all unless the rising and falling delays are perfectly matched. Alternatively, an edge can be transmitted through the new generate-and-reset delay stages if properly reset in time. A new delay-based clock generator adopting the delay stages is proposed on that account. It is attractive in that the maximum operating frequency can be comparable to that of the ring oscillator. Furthermore, the reset of the pulse in the delay stage cleans out the random noise as well, inhibiting any noise residue phenomenon.

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In this express, we propose Booth encoding high-speed modulo (2ⁿ − 2^p − 1) multipliers on the condition length of (Cout) ≤ min(2n − p, n + p), where Cout is the carry-out output of the carry save adder tree that is used to compress the partial products and the correction term after splitting, shifting and resetting. Synthesized results demonstrate that the proposed Booth encoding modulo (2ⁿ − 2^p − 1) multipliers have a good delay performance.

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An image processing chip includes many image processing engines requesting heavy external memory access. So bus traffic is a critical issue in real-time systems. An video encoder is one of blocks requesting the most heavy external memory access among them. This letter presents a method to reduce the external memory requests for accessing reference frames in video codec chips. The method pipelines a video in a frame level, and the intermediate reconstructed data is used in the next frame without storing it to external memory. Thereby the proposed algorithm reduces the external memory access with reasonable internal memory increase.

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In a previous paper, we proposed a simple method for measuring the mode excitation ratio in a two-mode fiber (TMF). Here, we experimentally investigate the applicability of the proposed method and also propose an alternative formulation to reduce experimental error.

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We present design of an asynchronous digital pipeline based on stochastic resonance gates (SR gates). These gates allow mismatch-tolerant and low-power designs by utilizing the beneficial role of noise (stochastic resonance effect). However, unpredictable delays appear in SR gates due to their dependence on stochastic processes. Therefore, applications are found in asynchronous circuits. We demonstrate the performance of a three-stage-asynchronous pipeline with dual-rail data encoding. Electrical simulations were done for a 0.18-µm CMOS technology, and confirmed the pipeline performance regardless of transistor mismatches and consuming low power (100 picowatts). Moreover, experimental results based on a macrosystem confirmed the pipeline performance.

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