IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Optimization of CMOS power-cell layout for improving junction breakdown
Ockgoo LeeJeonghu HanKyu Hwan AnHyoungsoo KimJoonhui HurKiseok YangKyutae LimChang-Ho LeeJoy Laskar
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JOURNALS FREE ACCESS

2014 Volume 11 Issue 19 Pages 20140523

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Abstract

Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-µm CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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