IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology
Liang BinDu YankangXu Hui
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JOURNALS FREE ACCESS

2014 Volume 11 Issue 19 Pages 20140710

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Abstract

A novel technique is proposed to mitigate the SERs of combinational circuits by using the half guard band. During the layout placement, by sharing the guard band between physically adjacent cells, the soft error rates (SERs) can be effectively reduced with less performance penalty. Three-dimensional technology computer-aided design (TCAD) numerical simulation and circuit-level simulation are adopted to demonstrate the hardening performance.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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