抄録
TDCs have been widely used to measure time intervals in various scientific, industrial, and portable electronics applications. To shorten the developing cycle of such digital systems, TDCs should be all-digital, flexible, and portable, and can be scalable to different processes. To achieve this, an all-digital cyclic time-to-digital converter (TDC) is proposed and described in synthesizable Verilog HDL code so that it can be built as an IP block. The proposed TDC uses a cyclic-delaying clock technique to reduce the error caused by the metastability of flip-flops and to simplify the control circuit and the compensation scheme to alleviate the need of continuous calibration. To confirm the functionality and performance, the proposed TDC has been simulated behaviorally based on the timing parameters obtained from HSPICE simulation. The LSB achieved is equal to the fastest loaded buffer delay of 13.87 ps in a 32-nm PTM and the proposed TDC has superior periodicity, high linearity, and a scalable dynamic range.
