A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

Abstract

This paper presents a low-voltage low-dropout voltage (LDO) regulator achieving a high power supply rejection (PSR) performance over a wide frequency range. A simple PSR enhancing circuit (PSRE) establishing a power noise (ripple) cancellation mechanism to avoid power noise passing through the power MOS transistor. A LDO regulator adopting the proposed PSRE was designed using a 1-V 90 nm CMOS process to convert an input of 1.2 V–0.8 V to an output of 0.85 V–0.5 V at a load current range of 0–100 mA. Post-layout simulations show that a PSR is above −57 dB at 1 MHz while the output spike during a 0.1 mA–100 mA load transient test is only 14 mV.