IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 20
Showing 1-14 articles out of 14 articles from the selected issue
REVIEW PAPER
  • Hiroki Morimura, Shoichi Oshima, Kenichi Matsunaga, Toshishige Shimamu ...
    Type: REVIEW PAPER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20142009
    Published: 2014
    Released: October 25, 2014
    JOURNALS FREE ACCESS
    This paper describes circuit techniques for energy-harvesting technology in millimeter-size ultra-low-power batteryless wireless sensor nodes as a front end for BigData, IoT, M2M, and ambient intelligence. Power generated by energy harvester becomes as small as the nanowatt level when the size of a sensor node becomes millimeter-size. First, technical trends in low-power circuits and the portfolio of energy harvesting and circuit technology are discussed from the viewpoints of technical and application issues. Then, circuit techniques for nanowatt level wireless sensor nodes — a zero-power vibration sensing circuit, power management with MEMS switch, and an intermitted RF transmitter — are explained.
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LETTER
  • Se-Hyu Choi, Keon-Jik Lee
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140713
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 03, 2014
    JOURNALS FREE ACCESS
    This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.
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  • In-Bok Kim, Hyun-Chul Choi, Kang Wook Kim
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 20 Pages 20140767
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 06, 2014
    JOURNALS FREE ACCESS
    In this paper, the design of a wideband bow-tie antenna using suspended stripline (SSL) balun is presented. The utilized balun is composed of a wideband multi-section power divider and a left-handed nonlinear transmission line (LH NLTL) implemented with SSL. The fabricated balun exhibits wide frequency bandwidth form 4 to 18 GHz (127%). To demonstrate applicability of the proposed balun, a modified bow-tie antenna is built and tested. The fabricated antenna provides wide frequency bandwidth from 5 to 18 GHz (110%) and the measured gain of typical 3.5 dBi with quasi-omni directional radiation patterns.
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  • Daqing Zheng, WeiMin Chen, Li Chen, Cunlong Li
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 20 Pages 20140791
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: September 30, 2014
    JOURNALS FREE ACCESS
    To solve the problems of the major kinds of microwave radars to meet the ranging needs of vibrating constructions, a new type of radar system for ranging is proposed based on the carrier modulation and heterodyne phase difference detecting with time-to-digital converter (TDC). In the radar system, an intermediate frequency (IF) signal is used to modulate the amplitude of radio frequency (RF) carrier signal to produce transmitting signal, and radar system receives the back-reflected signal from the target and demodulates the IF signal to expand the unambiguous range. Then, the heterodyne processing and phase detector with TDC device are adopted to detect phase shift of IF signal for ranging to improve the ranging resolution and ranging speed. In addition, the ranging experiment results proved the feasibility and validity of the presented radar system.
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  • Yingbo Zhao, Yintang Yang, Gang Dong
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140797
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: September 30, 2014
    JOURNALS FREE ACCESS
    This paper first proposes an impedance-level model of coupling channel between through silicon vias (TSVs) based on the two-port network theory. In order to get an accurate estimation of the coupling level from TSV-TSV in the early designing stage, we convert the impedance parameters of the model into the ABCD matrix to derive the formula of coupling coefficient, and the accuracy of the proposed formula is validated by comparing with 3D full-wave simulations. Furthermore, a design technique of optimizing the coupling between TSVs is proposed, and through SPICE simulations the proposed technique shows a desirable result to reduce the TSV-TSV coupling.
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  • Hiroshi Iwamura, Yukio Okazaki, Masahiro Kumagawa, Akinori Daimo, Koji ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140807
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 10, 2014
    JOURNALS FREE ACCESS
    In this paper, a new layout technique for improving drain efficiency of the switched capacitor power amplifier (SCPA) is proposed. To minimize the line length from the output capacitors to the output, capacitors and amplifiers are placed around the output pad. This reduces parasitic capacitances and resistances of the output line. Simulation result shows 3% improvement in the drain efficiency. The fabricated test chip achieves 24% drain efficiency at 7 dB back-off while delivering 11 dBm output.
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  • Chung-Hsun Huang, Wei-Chen Liao
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140820
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: September 30, 2014
    JOURNALS FREE ACCESS
    This paper proposes a compact programmable low dropout (LDO) regulator for an ultra-low voltage system-on-a-chip (SoC) using the voltage scaling technique. Two innovative design concepts were proposed: a programmable multi-level resistor array that can precisely tune the ratio of the feedback resistor divider; and a current limiter that limits a small static current flowing through the resistor network while reducing the occupied area. Experimental results show that the monotonic 50-step programmable output ranging from 0.3 V to 0.8 V is achieved, with an input of 1 V and a maximum load current of 100 mA. The occupied area is only 0.017 mm2.
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  • Xi Qu, Ze-kun Zhou, Bo Zhang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140824
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: September 30, 2014
    JOURNALS FREE ACCESS
    A low-power fast-transient on-chip low-dropout regulator (LDO) using advanced reference buffer is presented in this paper. The advanced reference buffer is proposed to provide the reference voltage of the LDO with more accurate level to improve the regulation performances. Moreover, in order to suppress the undershoot, the advanced reference buffer increases the reference voltage of the LDO abruptly when the output voltage decreases during transient state. Hspice simulation results show that the proposed LDO could deliver 100-mA load current with 0.8-V output voltage and 200-mV dropout voltage. By only consuming 1.8-µA quiescent current at light load, the undershoot, the overshoot and the settling time of the proposed LDO for load current switching from 100 µA to 100 mA with 300-ns edge time are about 60 mV, 80 mV and 1 µs, respectively.
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  • Tao Shan, Yahui Ma, Ran Tao, Shengheng Liu
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 20 Pages 20140872
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 10, 2014
    JOURNALS FREE ACCESS
    Sea clutter suppression is critical in the detection of low-velocity targets using a passive bistatic radar. The residual sea clutter may become high when the normalized least-mean-square (NLMS) algorithm with a small step size is used for this purpose. While a large step size can be used to reduce the residual sea clutter, it yields a widened filter notch, and thereby, causes significant target signal energy loss. A multi-channel NLMS algorithm is proposed to solve this problem, and its effectiveness is verified by simulation and real radar data analysis.
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  • Shao-Hua Chen, Ming-Bo Lin
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140875
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: September 30, 2014
    JOURNALS FREE ACCESS
    TDCs have been widely used to measure time intervals in various scientific, industrial, and portable electronics applications. To shorten the developing cycle of such digital systems, TDCs should be all-digital, flexible, and portable, and can be scalable to different processes. To achieve this, an all-digital cyclic time-to-digital converter (TDC) is proposed and described in synthesizable Verilog HDL code so that it can be built as an IP block. The proposed TDC uses a cyclic-delaying clock technique to reduce the error caused by the metastability of flip-flops and to simplify the control circuit and the compensation scheme to alleviate the need of continuous calibration. To confirm the functionality and performance, the proposed TDC has been simulated behaviorally based on the timing parameters obtained from HSPICE simulation. The LSB achieved is equal to the fastest loaded buffer delay of 13.87 ps in a 32-nm PTM and the proposed TDC has superior periodicity, high linearity, and a scalable dynamic range.
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  • Fang Liu, Yan Han, Yue Gao, Jun Sun
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140880
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 06, 2014
    JOURNALS FREE ACCESS
    An analog integrated maximum power point tracking (MPPT) controller which is suitable for distributed MPPT (DMPPT) topology is presented in this paper. Without large numbers of external circuit components, the DC/DC converter together with its MPPT controller can be made small enough to be integrated into the junction box, which is practical and cost effective for DMPPT topology. Besides a negative feedback loop is used in the proposed system to make the output voltage of PV panel less susceptible to fluctuations of irradiation intensity and interference of switching noise. Meanwhile, an improved P&O algorithm is adopted to achieve a fast and precise tracking especially in fast changing weather conditions. Furthermore, the tracking precision is higher than 99.5% under different external environmental conditions.
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  • Hu Jianguo, Duan Zhikui, Qin Junrui
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140882
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 03, 2014
    JOURNALS FREE ACCESS
    A reliable single-event upset (SEU) hardened latch is proposed to enhance the multiple nodes upset tolerance. By using the on-state transistor, half of the sensitive transistor pairs can be reduced compared to the typical DICE latch. Technology computer-aided design (TCAD) simulation is used to verify the hardening performance of our proposed latch.
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  • Zhiheng Wei, Keita Yasutomi, Shoji Kawahito
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140893
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 10, 2014
    JOURNALS FREE ACCESS
    This letter reports an extremely small differential non-linearity (DNL) in a cyclic analog-to-digital converter (ADC) using depletion-mode MOS (DMOS) capacitors for CMOS image sensors (CISs). Compared with conventional 1.5b digital-to-analog converter (DAC) configuration using 3 reference signals, the cyclic ADC with split sampling DMOS capacitors in the 1.5b DAC has the maximum DNL of +0.125/−0.125 LSB at 14b despite the large applied voltage dependency of the DMOS capacitors of 2.47%.
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  • Chung-Hsun Huang, Wei-Chen Liao, Chih-Ming Liao
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 20 Pages 20140906
    Published: 2014
    Released: October 25, 2014
    [Advance publication] Released: October 10, 2014
    JOURNALS FREE ACCESS
    This paper presents a low-voltage low-dropout voltage (LDO) regulator achieving a high power supply rejection (PSR) performance over a wide frequency range. A simple PSR enhancing circuit (PSRE) establishing a power noise (ripple) cancellation mechanism to avoid power noise passing through the power MOS transistor. A LDO regulator adopting the proposed PSRE was designed using a 1-V 90 nm CMOS process to convert an input of 1.2 V–0.8 V to an output of 0.85 V–0.5 V at a load current range of 0–100 mA. Post-layout simulations show that a PSR is above −57 dB at 1 MHz while the output spike during a 0.1 mA–100 mA load transient test is only 14 mV.
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