IEICE Electronics Express
Online ISSN : 1349-2543
Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS
Peng QinHao YanYangyang ZhouXiaoyong LiJianjun Zhou
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2014 Volume 11 Issue 24 Pages 20141062


This paper describes several phase noise suppression techniques for X-band (8–12 GHz) frequency synthesizer design in 65 nm CMOS technologies. A low noise voltage generator for varactor DC biasing is proposed to minimize its contribution to VCO phase noise, which minimizes the out-of-band phase noise. A crystal oscillator with low noise biasing is proposed to prevent bias and supply noise from deteriorating its output phase noise, which improves the in-band phase noise. A frequency synthesizer prototype was implemented in 65 nm CMOS technology and generates 8.6–12.4 GHz output frequencies, with a measured phase noise performance of −90 dBc/Hz and −110 dBc/Hz at 10-kHz (in-band) and 1-MHz (out-of-band) frequency offset, respectively. The prototype draws 33 mA current from a 1.2 V power supply and the core circuit area is 0.2 mm2. The performance comparison demonstrates the prototype achieves the best phase noise performance among all published frequency synthesizers in X-band or higher frequencies.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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