2014 Volume 11 Issue 3 Pages 20130912
This paper proposes a 2-stage variation-aware placement method that benefits from the optimality of a full-chipwise (chip-by-chip) placement to alleviate the impact of process variation. By classifying FPGAs into a small number of classes based on their variation maps and performing placement optimisation specifically for each class instead of each chip, two-stage placement can greatly reduce the execution time with similar timing improvement as achieved by full chipwise optimal placement. Our proposed method is implemented in a modified version of VPR 5.0 and verified using variation maps measured from 129 DE0 boards equipped with Cyclone III FPGAs. The results are compared with variation-blind, Statistical static timing analysis (SSTA) and full chipwise placement. The timing gain of 7.5% is observed in 20 MCNC benchmarks with 16 classes for 95% timing yield, while reducing execution time by a factor of 8 compared to full-chipwise placement.