IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 3
Showing 1-19 articles out of 19 articles from the selected issue
REVIEW PAPER
  • Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li
    Type: REVIEW PAPER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20142001
    Published: February 10, 2014
    Released: February 10, 2014
    JOURNALS FREE ACCESS
    This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and “good” device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.
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  • Tadaharu Minato, Katsumi Sato
    Type: REVIEW PAPER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 3 Pages 20142002
    Published: February 10, 2014
    Released: February 10, 2014
    JOURNALS FREE ACCESS
    As a FOM (Figure Of Merit), the power density of a power module has grown in an almost constant ratio for the past 20 years in the field of power electronics. This progress has been achieved by the joint development of power chips and a package. A combination of an IGBT (Insulated Gate Bipolor Transistor) and an FWD (Free Wheeling Diode) is the most frequent combination of power chips for a power module. The progress of both IGBT and diode is based not only upon the development of device structures but also upon the progress of the wafer process technology, which is derived from a LSI (Large Scale Integrated circuit) process and optimised for the power device. The package technology for power devices is uniquely developed for high reliability even for high power density application. This paper reports both the power chip and the package technologies up to the latest generation for the IGBT power module.
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  • Masayuki Ikebe
    Type: REVIEW PAPER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20142003
    Published: February 10, 2014
    Released: February 10, 2014
    JOURNALS FREE ACCESS
    Sensing systems perform digital-signal processing after converting analog input to digital output. These systems are used for various applications. This paper addresses the link between sensors and digital circuits. In particular, I address two areas: analog-to-digital converter (ADC) architecture and signal processing for sensing systems, and then describe their demands. Each circuit and system processing method was investigated and their basic outlines are illustrated. Finally, recent trends in specific hardware implementations of these algorithms are discussed.
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LETTER
  • Yan Liu, Guoqing Gu
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 3 Pages 20130748
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 22, 2014
    JOURNALS FREE ACCESS
    We propose an efficient method for labeling connected components in bi-level images. The proposed algorithm uses a Deterministic Finite Automaton to obtain chain codes and label component boundaries, and use a tracing technique that is simpler than existing methods. Experiments on various types of images show that the proposed method improves contour tracing efficiency.
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  • Toshiki Kanamoto, Hisato Inaba, Toshiharu Chiba, Yasuhiro Ogasahara
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20130813
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 15, 2014
    JOURNALS FREE ACCESS
    This paper suggests the modeling methods of non-uniform substrate resistivity for substrate resistance extraction. Conventional substrate model of uniform resistivity for each substrate layer can cause about 40-80% resistance extraction errors. Though model of simulated doping profile theoretically provides fine accuracy, the doping profile cannot be corrected with measurement results. The stepwise and interpolation models which this paper suggests enable 10% precision of resistance extraction and correction with measured resistance values. We also reveal that the modeling of the surface diffusion also gives large impact for resistance extraction of substrate and well.
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  • Kumar Narendra, Tee YewKok
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 3 Pages 20130824
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 24, 2014
    JOURNALS FREE ACCESS
    This paper introduces a new wide bandwidth Class E power amplifier providing high order harmonic suppression circuit. A design technique is presented on the methodology to achieve wideband high efficiency performance while preserving high harmonic suppression. A prototype board demonstrated drain efficiency of 70% and second harmonic rejection of more than 84dBc (as well as higher harmonics), and output power level more than 6.5W with ±0.5dB power flatness, across VHF band (136-174MHz). Simulations of power performance (i.e. efficiency and output power) were verified by measurements, and good agreements were obtained.
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  • Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George Constantinid ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20130912
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: December 05, 2013
    JOURNALS FREE ACCESS
    This paper proposes a 2-stage variation-aware placement method that benefits from the optimality of a full-chipwise (chip-by-chip) placement to alleviate the impact of process variation. By classifying FPGAs into a small number of classes based on their variation maps and performing placement optimisation specifically for each class instead of each chip, two-stage placement can greatly reduce the execution time with similar timing improvement as achieved by full chipwise optimal placement. Our proposed method is implemented in a modified version of VPR 5.0 and verified using variation maps measured from 129 DE0 boards equipped with Cyclone III FPGAs. The results are compared with variation-blind, Statistical static timing analysis (SSTA) and full chipwise placement. The timing gain of 7.5% is observed in 20 MCNC benchmarks with 16 classes for 95% timing yield, while reducing execution time by a factor of 8 compared to full-chipwise placement.
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  • Kai Jing, Yiqi Zhuang, Huaxi Gu
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20130928
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 20, 2014
    JOURNALS FREE ACCESS
    A new design is presented that combines a low-noise amplifier (LNA) with a new passive base-collector notch filter based on Jazz 0.18μm SiGe technology. Extra capacitor is introduced in notch filter, eliminating the operating-frequency input mismatch in formal base-collector notch filters. Results show that LNA obtains a 4dB S21 enhancement of 14.1dB and a 7dB increase S11 of −15dB at 20.5GHz, image rejection ratio is 33.5dB. IIP3 is 3.43dBm at the operating frequency for a power consumption of 18mW from a 3V power supply.
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  • Dongeun Lee, Jaesik Choi, Heonshik Shin
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 3 Pages 20130947
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 14, 2014
    JOURNALS FREE ACCESS
    Compressive sensing (CS) with sparse random matrix for the random sensing basis reduces source coding complexity of sensing devices. We propose a downsampling scheme to this framework in order to further reduce the complexity and improve coding efficiency simultaneously. As a result, our scheme can deliver significant gains to a wide variety of resource-constrained sensors. Experimental results show that the computational complexity decreases by 99.95% compared to other CS framework with dense random measurements. Furthermore, bit-rate can be saved up to 46.29%, by which less bandwidth is consumed.
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  • Hyuek Jae Lee
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 3 Pages 20130972
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 14, 2014
    JOURNALS FREE ACCESS
    This paper aims to demonstrate experimentally a new all-optical non-return-to-zero (NRZ) to return-to-zero (RZ) data format reconversion from the red-chirped NRZ signal, generated by the RZ-to-NRZ converter, using a semiconductor optical amplifier in a fiber loop mirror (so-called an SOA-loop-mirror). The primary merit of the proposed NRZ-to-RZ reconversion is that no additional optical clock is required in the process, unlike other conventional methods. While the optical power penalty for the RZ-to-NRZ conversion using an SOA-loop-mirror was 1.64dB, the proposed NRZ-to-RZ reconversion penalty was 0.6dB compared to that of the original input RZ signal.
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  • M Poongothai, A Rajeswari, V Kanishkan
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20130975
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 14, 2014
    JOURNALS FREE ACCESS
    In this paper a Heuristic Based Improved Linearly Decreasing Weight Particle Swarm Optimization algorithm (ILDW- PSO) is proposed to solve real time task assignment in heterogeneous processors. To achieve better quality solution to the particles, existing LDW-PSO encompasses to ILDW- PSO, which includes Genetic algorithm mutation operator. The objective is to minimize the maximum utilization of the processors with energy aware load balance condition which reduces the energy consumption. Experimental results show that ILDW-PSO outperforms the existing PSO algorithms interms of maximum utilization and normalized energy consumption for both consistent utilization matrix and inconsistent utilization matrix.
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  • Hiroyuki Takahashi, Akihiko Hirata, Katsuhiro Ajito, Shintaro Hisatake ...
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2014 Volume 11 Issue 3 Pages 20130989
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 14, 2014
    JOURNALS FREE ACCESS
    A 120-GHz-band close-proximity wireless system that achieves the first 10-Gbit/s real-time transmission satisfying the regulation for extremely low-power radio stations (ELRS regulation). The use of photonic technologies enables the transmitter to perform 10-Gbit/s quadrature-phase-shift keying (QPSK) modulation and generate an RF spectrum with negligibly small spurious signals. The phase of the emitted signal fluctuates with changes in the external environment, which interferes with the demodulation using a reference signal. To overcome phase fluctuation at the transmitter, we use differentially coherent detection for the demodulation. We verified that the level of the measured RF spectrum of the integrated transmitter was below the level defined by the ELRS regulation. The transmitter and the receiver demonstrated error-free wireless transmission over a distance of 10mm with a link margin of 11dB.
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  • Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20130992
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 15, 2014
    JOURNALS FREE ACCESS
    A novel area-efficient dual replica-bitline delay technique is proposed in this brief to improve process-variation-tolerance of low voltage SRAM application. This strategy suppresses the timing variation by adding one another replica-bitline and introducing novel replica cell which has the same size as conventional. Simulation results in TSMC 65nm LP technology show that more than 32.3% timing variation is reduced and 18% cycle time is saved at low supply voltage without any area overhead.
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  • Jeong-Geun Park, Che-Young Kim
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 3 Pages 20131000
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 15, 2014
    JOURNALS FREE ACCESS
    This article proposes a substrate integrated coaxial line (SICL) structure with composite right left handed (CRLH) characteristics. The CRLH characteristics were implemented by inserting an inter-digital capacitor (IDC) and strip line into the SICL. To verify the proposed CRLH structure, the effective parameters (εeff, μeff), refractive index (n), propagation constant (β) and Bloch impedance (ZB) were derived using the retrieved effective parameter method, from which left-handed (LH), right-handed (RH), zeroth-order resonance (ZOR) characteristics were confirmed. After completing the CRLH-equivalent circuit from the effective parameters, the component values were validated by comparing the results of a simulation model and a circuit model. The simulation results agreed well with the measured results. This confirmed that the proposed SICL is a balanced CRLH SICL unit cell.
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  • Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro H ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20131006
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 15, 2014
    JOURNALS FREE ACCESS
    A parallel-serial-combined search scheme, which performs a multi-bit-by-multi-bit parallel-serial search for a single search, is proposed for a magnetic tunnel junction (MTJ)-based high-density and energy-efficient nonvolatile ternary content-addressable memory (TCAM). A two transistor and two MTJ device (2T-2MTJ)-based TCAM cell circuit can be utilized for a bit-parallel search operation up to 4bits under random variations of MOS and MTJ device characteristics by amplifying the multi-bit cell-array resistance difference owing to the source-degeneration cell structure in combination with the cascode structure of the pre-amplification stage in the word circuit. In the proposed parallel-serial-combined search scheme, the bit length of a parallel operation in a single cycle and the search cycle count are optimized, so that the cell activity is minimized by tuning the trade-off between power consumption and search speed. When the proposed nonvolatile TCAM performs a variable-bit parallel-serial-combined search, the cell activity of the proposed nonvolatile TCAM is reduced to 60% of that of a conventional bit-parallel nonvolatile TCAM with a three-level segmentation scheme, which indicates higher density and higher energy efficiency with acceptable search speed.
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  • Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, Shu-Syun Jhao
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20131011
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 14, 2014
    JOURNALS FREE ACCESS
    An all-digital on-chip delay measurement (OCDM) architecture with high delay measurement resolution and low supply voltage sensitivity for efficiently detection and diagnosis in the high performance system-on-chip (SoC) applications is presented. Based on the proposed differential delay line pair (DDLP) and an cascade-stage delay line, the quantization resolution of the proposed OCDM not only has a high immunity to supply voltage variations without an extra self-biasing or calibration circuit, but also achieves to several picoseconds. Simulation results show that delay measurement resolution can be improved to 1.04ps, and the average delay resolution variation is 11fs with ±10% supply voltage variations. In addition, the proposed design can be implemented in all-digital design manner, making it very suitable for SoC applications as well as system-level integration.
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  • Wang Yong, Ge Jianhua, Ai Bo
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 3 Pages 20131044
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 24, 2014
    JOURNALS FREE ACCESS
    In this paper, we propose a robust adaptive predistortion (PD) scheme based on a hybrid direct learning (HDL) structure for mitigating the effects of measurement noise derived from the feedback path of power amplifier (PA). In particular, by means of an additional gradient adaptive term, a modified normalized least mean square (MNLMS) algorithm was developed to identify the coefficients of PA forward model with relative long-term memory in the noisy feedback environments. The performance of this PD scheme is validated with numerical simulations.
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  • Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George Constantinid ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20140011
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 24, 2014
    JOURNALS FREE ACCESS
    In this paper, the FPGA routing process is explored to mitigate and take advantage of the effect of delay variability due to process variation. A new method called partial rerouting is proposed in this paper to improve the timing performance based on process variation and reduce the execution time. By only rerouting a small number of critical and near-critical paths, about 6.3% timing improvement can be achieved by partial rerouting method. At the same time, partial rerouting can speed up the routing process by 9 times compared with full chipwise with 100 target FPGAs (variation maps). Moreover, the partial rerouting enables a trade-off between product yield and routing speed.
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  • Youngil Kim, Sangsun Lee
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 3 Pages 20140012
    Published: February 10, 2014
    Released: February 10, 2014
    [Advance publication] Released: January 27, 2014
    JOURNALS FREE ACCESS
    This letter describes a H/V linear regulator for enhancing power supply rejection (PSR) for generating the program/erase voltage. In order to reduce the ripple voltage of the H/V linear regulator, using an additional feedback technique is proposed. The proposed H/V linear regulator has dual loop feedback that improves loop gain and PSR. In the simulated PSR performance, −43.1dB is observed with the proposed H/V linear regulator at 2.12MHz. This result is 13dB better than results obtained with the conventional H/V Linear regulator.
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