High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications

Abstract

An all-digital on-chip delay measurement (OCDM) architecture with high delay measurement resolution and low supply voltage sensitivity for efficiently detection and diagnosis in the high performance system-on-chip (SoC) applications is presented. Based on the proposed differential delay line pair (DDLP) and an cascade-stage delay line, the quantization resolution of the proposed OCDM not only has a high immunity to supply voltage variations without an extra self-biasing or calibration circuit, but also achieves to several picoseconds. Simulation results show that delay measurement resolution can be improved to 1.04ps, and the average delay resolution variation is 11fs with ±10% supply voltage variations. In addition, the proposed design can be implemented in all-digital design manner, making it very suitable for SoC applications as well as system-level integration.