Mitigation of process variation effect in FPGAs with partial rerouting method

抄録

In this paper, the FPGA routing process is explored to mitigate and take advantage of the effect of delay variability due to process variation. A new method called partial rerouting is proposed in this paper to improve the timing performance based on process variation and reduce the execution time. By only rerouting a small number of critical and near-critical paths, about 6.3% timing improvement can be achieved by partial rerouting method. At the same time, partial rerouting can speed up the routing process by 9 times compared with full chipwise with 100 target FPGAs (variation maps). Moreover, the partial rerouting enables a trade-off between product yield and routing speed.