Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells

Abstract

The effect of charge sharing on single event upset (SEU) sensitive area of SRAM cells is studied in a 40-nm bulk CMOS technology. All transistors in a 6T SRAM cell are simulated in 3D TCAD models, and SEU sensitive areas are measured in different simulation conditions. We find the charge sharing can reduce SEU sensitive area of SRAM cells. The effect of charge sharing on radiation sensitivity of both PMOS and NMOS are analyzed in depth. The works in this paper can guide the single event rate prediction and the hardened design of SRAMs in advanced technologies.