IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 4
Showing 1-9 articles out of 9 articles from the selected issue
LETTER
  • Kwang Jin Kim, Byung Hee Son, Bruce Burgess, Sung Wan Bang, Jeong Woo ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 4 Pages 20130939
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    A relative position indicator (RPI) system with radial antenna array (RAA) is proposed and experimentally demonstrated for use in a tracking-based position estimation system (PES). Utilizing radial vectors generated by both received signal strength (RSS) and azimuth direction of each antenna element in the RAA, accurate direction and distance-to-target can be obtained simultaneously. The proposed RPI system using a radial vector sum and a simple equalization process can mitigate the gain mismatch problem, which was a serious problem in previous tracking-based PESs.
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  • Dong Wang, Peng Cao, Yang Xiao
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 4 Pages 20130981
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    A parallel arithmetic array processor for accelerating compute-intensive applications in low-power embedded systems is proposed in this study. The proposed flexible hardware architecture enables the fast execution of both control-dominated and compute-centric streaming computation tasks on the same array. Consequently, multiple levels of parallelism can be efficiently exploited. A test chip integrated with two 16×16 array processor cores was implemented in 65nm CMOS technology. Multi-format video decoding algorithms were mapped on the chip as benchmarks. The proposed architecture achieved a notable 2.8× advantage on performance over an industrial coarse-grained array processor and a 66% performance boost over a state-of-the-art many-core processor. Meanwhile, the energy-efficiency was improved by 15.3× and 1.78×, respectively.
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  • Kaifeng Zhang, Huanzhang Lu, Weidong Hu, Jian Wang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 4 Pages 20131003
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    The paper presents an evolvable system for intrinsic hardware evolution based on look-up-table (LUT) manipulation. We also introduce dynamic routing using multiplexer to improve the flexibility of the system. The proposed approach is implemented on Xilinx ML403 Evaluation Platform, and an evolution of 3-bit multiplier is employed for verification. The experimental results show that more than three orders of evolution speed enhancement over JBits and one order of evolution speed enhancement over bitstream reverse engineering (BRE) based methods is achieved.
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  • Wonkyeong Park, Van Ha Nguyen, Kilsoo Seo, Hanjung Song
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 4 Pages 20131012
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    This letter presents a new digital controller (DCL) with a new dimming method for high power-factor LED driver circuits. The core of proposed digital controller is based on a zero-voltage (ZVD) detection and a digital sine generator (DSG). By using the DSG, an effective dimming can be carried out easily. The proposed DCL was simulated and fabricated using the 1μm-650V DMOS process. The results obtained indicate that the inductor current waveform is in phase with the input voltage to gain a high power factor, because the inductor current is synchronized to the zero voltage signal from ZVD as expected. Also, the LED current changes according to the reference voltage, which is controlled by an external switch that adjusts the brightness of the LED.
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  • Xiaopeng Liu, Yan Han, Bin Zhang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 4 Pages 20131029
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    A Triple-modular redundancy (TMR) system will have a failure if Single Event Transient (SET) faults affect the voter. In this paper, we propose a full SET-tolerance dual-modular majority voter (DMV) circuit for all internal nodes. The DMV consisting of two simplex-modular voters, two inverters, a C-element inverter and a weak keeper is implemented in CMOS 40nm technology. A novel XOR gate and a multiplexer based voter is also presented and used as a simplex-modular voter so that the whole DMV can be implemented by 40 CMOS transistors. A novel C-element weak keeper is also proposed to reduce power consumption. Monte-Carlo simulation results show that power consumption of DMV only increases by 11.09% compared to that of a single traditional voter.
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  • Leyu Zhai, Haitao Zhai, Ziwei Zhou, Eryang Zhang, Kai Gao
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2014 Volume 11 Issue 4 Pages 20131030
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    This paper proposes a recursive optimum-term selecting (ROS) approach to pruning the general Volterra series, by which we can achieve a custom-tailored model to characterize nonlinearity of wideband power amplifiers (PAs) with memory effects. The achieved model is more suitable for the individual PA than those static models, such as the MP and GMP models, as it selects the most efficient terms from the general Volterra series based on the theory of recursive correlation cancellation. Simulation results show that the approach is effective, and the pruned model developed by the proposed approach is efficient as well as adaptable.
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  • Xiao Zhao, Qisheng Zhang, Ming Deng
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 4 Pages 20131040
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    A novel bulk-driven technique is adopted to improve the gain-bandwidth of the conventional recycling current OTA, without requiring any additional power dissipation. Also, the threshold voltage of the transistors is reduced because of bulk-biasing technique, leading to the input/output voltage range extended. To compare the performance advantages of the proposed OTA versus the conventional one, two OTAs were designed in a 1-V 0.18µm CMOS process. Results show that the proposed OTA’s unit-gain bandwidth is improved by 55% and the input/output voltage range is increased by 140/110mV. Also, the dc gain is enhanced almost 6dB.
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  • Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 4 Pages 20131041
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    In this work, a three-dimensional (3-D) architecture of one-time programmable (OTP) nonvolatile memory (NVM) arrays is introduced and its viable process integration and operation method are schemed. Vertical stack architecture is highly persued for higher-level integration and NVMs based on devices free from transistors and charge trapping layers would be one of the candidates. In this work, in an effort for the NVM technology trend, architecture, fabrication process, and operation scheme for faster data access are studied in depth. Silicon (Si) pn-junction diode is focused by its virtues of cost-effectiveness, process maturity, and compatibility to peripheral Si CMOS circuits.
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  • Peng Li, Minxuan Zhang, Weicheng Zhang, Zhenyu Zhao, Chao Song, Hua Fa ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 4 Pages 20140051
    Published: February 25, 2014
    Released: February 25, 2014
    [Advance publication] Released: January 31, 2014
    JOURNALS FREE ACCESS
    The effect of charge sharing on single event upset (SEU) sensitive area of SRAM cells is studied in a 40-nm bulk CMOS technology. All transistors in a 6T SRAM cell are simulated in 3D TCAD models, and SEU sensitive areas are measured in different simulation conditions. We find the charge sharing can reduce SEU sensitive area of SRAM cells. The effect of charge sharing on radiation sensitivity of both PMOS and NMOS are analyzed in depth. The works in this paper can guide the single event rate prediction and the hardened design of SRAMs in advanced technologies.
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