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IEICE Electronics Express
Vol. 11 (2014) No. 5 pp. 20130983

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http://doi.org/10.1587/elex.11.20130983

LETTER

A packet memory controller in routers accesses the packet memory according to the QoS requirements of packets. The previous QoS-aware controller using a feedback control loop degenerates into round robin scheduling under temporary overload and suffers from slow response. We propose a new packet memory controller that estimates input load accurately and rapidly and schedules different classes using a flexible bitmap scheduler. The results show that under temporary overload or rapidly changing input loads, it can successfully meet the latency requirements by showing only less than 2% difference from the requirement of the high priority class.

Copyright © 2014 by The Institute of Electronics, Information and Communication Engineers

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