IEICE Electronics Express
Online ISSN : 1349-2543
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Parallel graph traversal for FPGA
Shice NiYong DouDan ZouRongchun LiQiang Wang
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2014 Volume 11 Issue 7 Pages 20130987

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Abstract

This paper presents a multi-channel memory based architecture for parallel processing of large-scale graph traversal for field-programmable gate array (FPGA). By designing a multi-channel memory subsystem with two DRAM modules and two SRAM chips and developing an optimized pipelining structure for the processing elements, we achieve superior performance to that of a state-of-the-art highly optimized BFS implementations using the same type of FPGA.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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