IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 11 , Issue 7
Showing 1-6 articles out of 6 articles from the selected issue
LETTER
  • Shice Ni, Yong Dou, Dan Zou, Rongchun Li, Qiang Wang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 7 Pages 20130987
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    This paper presents a multi-channel memory based architecture for parallel processing of large-scale graph traversal for field-programmable gate array (FPGA). By designing a multi-channel memory subsystem with two DRAM modules and two SRAM chips and developing an optimized pipelining structure for the processing elements, we achieve superior performance to that of a state-of-the-art highly optimized BFS implementations using the same type of FPGA.
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  • Song Hyun Jo, Yong Ho Song
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 7 Pages 20140027
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    HEVC is a video codec which yields higher coding efficiency compared to its predecessors. This efficiency improvement has been realized by adopting many advanced algorithms to its coding tools which often require a huge amount of computation. Beside, HEVC is designed to be applicable mainly to high resolution videos that necessitate the enormous amount of computation. One common solution to this problem is to execute the algorithms in a parallelized way. However, the data dependency between neighboring coding tree units, the basic decoding unit in HEVC, limits the level of parallelization in Intra Prediction. This paper proposes a dependency reduction technique which identifies virtual dependencies among coding tree units via runtime analysis and eliminates them to enhance potential parallelism. The experimental results show that the performance of Intra Prediction can be significantly improved by lifting such virtual dependencies
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  • Yi Liu, Shuai Ma, Yintang Yang, Zhangming Zhu
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 7 Pages 20140038
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 06, 2014
    JOURNALS FREE ACCESS
    In this letter, a capacitively charge-sharing transmitter (CCS) is proposed as a novel design to replace the traditional differential capacitive pre-emphasis transmitter (CPE), for the purpose of reducing the dynamic power consumption by half. The CCS functions as a transmitter for mesh NoC links to achieve high-speed and low-power transmission. CCS generates a pair of differential low-swing signals at a time through charge-sharing. Its capacitively driven mode enables high-speed transmission and provides pre-emphasis to extend the bandwidth. Simulation shows that CCS can achieve 9Gb/s data rate over 2mm twisted differential interconnects with only 56.4fJ/b power consumption. With a clockless hysteresis receiver, the transceiver for NoC links enables a data rate of 7Gb/s with at least 70% eye-opening while consumes only 90.8fJ/b.
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  • Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, Jin-Ku Kang
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 7 Pages 20140088
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 24, 2014
    JOURNALS FREE ACCESS
    This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13μm CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17ps on 25−1 PRBS input pattern compared to 26ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3mW with the proposed BBPD.
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  • Sichen Yu, Zhonghan Shen, Xiaolu Liu, Huixiang Han, Xi Tan, Na Yan, Ha ...
    Type: LETTER
    Subject area: Integrated circuits
    2014 Volume 11 Issue 7 Pages 20140138
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    A digital intensive Clock Recovery Circuit applied to HF-Band active RFID tag is proposed in this paper. Based on the signal interface of ISO/IEC 14443 Type-A protocol, in order to achieve the coherent demodulation in receiving mode, a modified digital intensive PLL is utilized to accurately extract the carrier's frequency and phase information from the received ASK 100% modulation signal. Meanwhile, in transmitting mode, the proposed PLL can also effectively calibrate the system clock's frequency error and phase deviation in a discontinuous mode. The whole chip of Clock Recovery Circuit was implemented in 180nm EEPROM technology. The measurement results show that the maximum power consumption of Clock Recovery Circuit is about 900μW at 1.8V power supply, and the phase deviation in the demodulation and modulation period is respectively less than 10° and 20°.
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  • Jianfeng Dai, Jinbin Zhao, Keqing Qu, Ming Lin
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2014 Volume 11 Issue 7 Pages 20140145
    Published: April 10, 2014
    Released: April 10, 2014
    [Advance publication] Released: March 14, 2014
    JOURNALS FREE ACCESS
    Based on inductor current ripple and output voltage ripple to charge and discharge for capacitor C, a fast hysteresis control strategy is proposed in this paper. It is not only simple and solves the compensation problem of the error amplifier in conventional voltage PWM control, but also provides better transient response and stability to meet the challenges of the buck converter. Finally, the steady-state operation of the proposed control strategy is analyzed and verified by simulation and experimental results.
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